diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-21 20:06:10 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-21 20:06:10 +0000 |
| commit | 9839cbd53fdcfcee52c406d9f52af924192e618d (patch) | |
| tree | a38daaa0b545aaf36a7ad5f5df9dfe73e08d97da /src/northbridge/amd | |
| parent | cf036d1266d7ec307aac437105b094acbc9681ec (diff) | |
| download | coreboot-9839cbd53fdcfcee52c406d9f52af924192e618d.tar.xz | |
* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/gx2/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/northbridge.c | 14 |
3 files changed, 7 insertions, 11 deletions
diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig index 3dc5b9a56c..4fa7ea6543 100644 --- a/src/northbridge/amd/gx2/Kconfig +++ b/src/northbridge/amd/gx2/Kconfig @@ -19,4 +19,6 @@ config NORTHBRIDGE_AMD_GX2 bool + # for VSM: + select PCI_OPTION_ROM_RUN_REALMODE diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index 75a93a148d..b6fd816d2e 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -1,6 +1,8 @@ config NORTHBRIDGE_AMD_LX bool select HAVE_HIGH_TABLES + # for VSM: + select PCI_OPTION_ROM_RUN_REALMODE config VIDEO_MB int diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 137f7a9d09..4dd29d134f 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -74,11 +74,8 @@ #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} -extern void graphics_init(void); -extern void cpubug(void); -extern void chipsetinit(void); - -void setup_realmode_idt(void); +void print_conf(void); +void graphics_init(void); void do_vsmbios(void); struct msr_defaults { @@ -319,7 +316,7 @@ static void northbridge_init(device_t dev) //printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); } -void northbridge_set_resources(struct device *dev) +static void northbridge_set_resources(struct device *dev) { struct resource *resource, *last; unsigned link; @@ -426,7 +423,6 @@ static void pci_domain_set_resources(device_t dev) static void pci_domain_enable(device_t dev) { - printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); // do this here for now -- this chip really breaks our device model @@ -434,14 +430,10 @@ static void pci_domain_enable(device_t dev) cpubug(); chipsetinit(); - setup_realmode_idt(); - - printk(BIOS_DEBUG, "Before VSA:\n"); // print_conf(); do_vsmbios(); // do the magic stuff here, so prepare your tambourine ;) - printk(BIOS_DEBUG, "After VSA:\n"); // print_conf(); graphics_init(); |