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| author | Marc Jones <marcj303@gmail.com> | 2009-05-14 23:42:41 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2009-05-14 23:42:41 +0000 |
| commit | 99fd2a3b3ac587498b551c2c6e5d6d20f646e65b (patch) | |
| tree | 2c82d99a8b7ec6162393ec5dd5003f22e4d2f269 /src/northbridge/amd | |
| parent | 9ea1e0c18a44abb17497a30557a61dda25ec2922 (diff) | |
| download | coreboot-99fd2a3b3ac587498b551c2c6e5d6d20f646e65b.tar.xz | |
Update equivalent processor revision ID to load latest microcode patches and
register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Vincent Lim (vincent.lim@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdfam10/raminit_amdmct.c | 3 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/amddefs.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 9696689281..fd967b5ebf 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -149,6 +149,9 @@ u32 mctGetLogicalCPUID(u32 Node) case 0x10023: ret = AMD_DR_B3; break; + case 0x10062: + ret = AMD_RB_C2; + break; default: /* FIXME: mabe we should die() here. */ print_err("FIXME! CPU Version unknown or not supported! \n"); diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 6ff9d02b34..5afb0a3c1d 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -40,6 +40,7 @@ #define AMD_DR_B2 0x00200000 /* Barcelona B2 */ #define AMD_DR_BA 0x00400000 /* Barcelona BA */ #define AMD_DR_B3 0x00800000 /* Barcelona B3 */ +#define AMD_RB_C2 0x01000000 /* Shanghai C2 */ /* * Groups - Create as many as you wish, from the above public values @@ -57,6 +58,8 @@ #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2) +#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) /* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE |