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authorYinghai Lu <yinghailu@gmail.com>2005-01-21 22:02:09 +0000
committerYinghai Lu <yinghailu@gmail.com>2005-01-21 22:02:09 +0000
commitb5d9af41053f2cd66503b6e8a58676e97a3bbf85 (patch)
tree6fae40daf38f1f9aac39beff6c6dbd64492e6862 /src/northbridge/amd
parente324731152fa1a64aa210c1f40b8b2afa3dc1623 (diff)
downloadcoreboot-b5d9af41053f2cd66503b6e8a58676e97a3bbf85.tar.xz
move apic cluster before pci_domain in MB Config.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c18
1 files changed, 16 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 4136f9f27c..6fd4cf96ce 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -741,8 +741,22 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
device_t dev, cpu;
struct device_path cpu_path;
- /* Find the cpu's memory controller */
- dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
+ /* Find the cpu's memory controller */
+ dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+ if(!dev) {
+ // in case in mb Config.lb we move apic cluster before pci_domain and not set that for second CPU
+ struct device dummy;
+ uint32_t id;
+ dummy.bus = dev_mc->bus;
+ dummy.path.type = DEVICE_PATH_PCI;
+ dummy.path.u.pci.devfn = PCI_DEVFN(0x18 + i, 3);
+ id = pci_read_config32(&dummy, PCI_VENDOR_ID);
+ if (id != 0xffffffff && id != 0x00000000 &&
+ id != 0x0000ffff && id != 0xffff0000) {
+ //create that for it
+ dev = alloc_dev(dev_mc->bus, &dummy.path);
+ }
+ }
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;