diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 00:18:43 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 00:18:43 +0000 |
| commit | 0e5d3e16b494aafa3c08a28a0484ee0845d84512 (patch) | |
| tree | 72f4d401f94bfb0f2041f994533faa7ba4207588 /src/northbridge/amd | |
| parent | adb23a51f5f711d10798a0bcddf4764a5dc0ae7c (diff) | |
| download | coreboot-0e5d3e16b494aafa3c08a28a0484ee0845d84512.tar.xz | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdfam10/Kconfig | 8 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 10 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/amddefs.h | 4 |
3 files changed, 20 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 8fc2653d02..74e0ff454b 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -112,4 +112,12 @@ if DIMM_DDR3 endif endif +config SVI_HIGH_FREQ + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + help + Select this for boards with a Voltage Regulator able to operate + at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. + source src/northbridge/amd/amdfam10/root_complex/Kconfig diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 7e102790ab..2ef46ffe9e 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -198,11 +198,19 @@ #define PVI_MODE 0x100 /* PviMode bit mask */ #define VID_SLAM_OFF 0x0dfffffff /* set VidSlamMode OFF */ #define VID_SLAM_ON 0x020000000 /* set VidSlamMode ON */ +#define NB_PSTATE_FORCE_ON 0x010000000 /* set Northbridge P-state + force on next LDTSTOP + assertion on, in F3xA0 */ +#define BP_INS_TRI_EN_ON 0x00004000 /* breakpoint pins tristate + enable in F3xA0 */ #define PLLLOCK_OFF 0x0ffffc7ff /* PllLockTime Mask OFF */ #define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */ #define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */ -/* P-state Specification register base in PCI sapce */ +#define SVI_HIGH_FREQ_ON 0x00000200 /* F3xA0[SviHighFreqSel] for + 3.4 MHz SVI in rev. C3 */ + +/* P-state Specification register base in PCI space */ #define PS_SPEC_REG 0x1e0 /* PS Spec register base address */ #define PCI_REG_LEN 4 /* PCI register length */ #define NB_DID_MASK 0x10000 /* NbDid bit mask */ diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 997100bc8f..0e7319bb25 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -64,7 +64,9 @@ #define AMD_DR_ALL (AMD_DR_Bx) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 ) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) -#define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) +#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) +#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) +#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) #define AMD_DR_Dx (AMD_HY_D0) #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) |