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| author | Yinghai Lu <yinghailu@gmail.com> | 2005-01-07 21:12:05 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2005-01-07 21:12:05 +0000 |
| commit | 90a04ee5a93c0e99cbc46febf5556be6affef03b (patch) | |
| tree | ef83c89ee92664f589435201f83374fce0a0419b /src/northbridge/amd | |
| parent | 31ce35e8ab42cd051c660ed752febc89632e92c6 (diff) | |
| download | coreboot-90a04ee5a93c0e99cbc46febf5556be6affef03b.tar.xz | |
enable apic ext id to keep bsp using 0
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/northbridge.c | 22 |
2 files changed, 20 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index e056f53da7..db6ffc8128 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -145,7 +145,7 @@ static void enable_apic_ext_id(u8 node) u32 val; val = pci_read_config32(NODE_HT(node), 0x68); - val |= HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST ; + val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); pci_write_config32(NODE_HT(node), 0x68, val); #endif } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5534a11371..16f8919ced 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -712,11 +712,24 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_cf8_conf1, }; +#define APIC_ID_OFFSET 0x10 + static unsigned int cpu_bus_scan(device_t dev, unsigned int max) { struct bus *cpu_bus; + device_t dev_mc; int i; - int apic_id_offset = lapicid(); // bsp apicid + int enable_apic_ext_id = 0; + int bsp_apic_id = lapicid(); // bsp apicid + int apic_id_offset = bsp_apic_id; + + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if(pci_read_config32(dev_mc, 0x68) & ( HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST)) { + enable_apic_ext_id = 1; + if(apic_id_offset==0) { //bsp apic id is not changed + apic_id_offset = APIC_ID_OFFSET; + } + } /* Find which cpus are present */ cpu_bus = &dev->link[0]; @@ -751,8 +764,11 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) /* Report what I have done */ if (cpu) { - if(cpu->path.u.apic.apic_id<apic_id_offset) { - cpu->path.u.apic.apic_id += apic_id_offset; + if(enable_apic_ext_id) { + if(cpu->path.u.apic.apic_id<apic_id_offset) { //all add offset except bsp cores + if( (cpu->path.u.apic.apic_id > siblings) || (bsp_apic_id!=0) ) + cpu->path.u.apic.apic_id += apic_id_offset; + } } printk_debug("CPU: %s %s\n", dev_path(cpu), cpu->enabled?"enabled":"disabled"); |