summaryrefslogtreecommitdiff
path: root/src/northbridge/amd
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2018-10-30 07:07:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-05 09:05:33 +0000
commitd35c7fe1bff55471c62b11d208cf3a71dec30d6d (patch)
treecbae0c724c9632088998e9ff401f212ec960e6b5 /src/northbridge/amd
parentc4ba0f4cbdd28a8e8339085f56340a5f880014c2 (diff)
downloadcoreboot-d35c7fe1bff55471c62b11d208cf3a71dec30d6d.tar.xz
amd/mtrr: Fix IORR MTRR
IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29352 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdmct/mct/mctdqs_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c6
2 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 5aadcccf56..75fc8a427e 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -816,10 +816,10 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
+ _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
- _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
}
@@ -829,7 +829,7 @@ void ResetTargetWTIO_D(void)
hi = 0;
lo = 0;
- _WRMSR(0xc0010017, lo, hi); // IORR0 Mask
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); // IORR0 Mask
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 8b6a8d41bc..7920e656f5 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -2148,10 +2148,10 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
+ _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
- _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
}
void ResetTargetWTIO_D(void)
@@ -2160,7 +2160,7 @@ void ResetTargetWTIO_D(void)
hi = 0;
lo = 0;
- _WRMSR(0xc0010017, lo, hi); /* IORR0 Mask */
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
}
u32 SetUpperFSbase(u32 addr_hi)