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| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/northbridge/amd | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
| download | coreboot-00c8c4a31632150fa711493f39e727da950ebe9f.tar.xz | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdk8/reset_test.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index b775813c53..bee3faa0ce 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -44,7 +44,8 @@ static inline void distinguish_cpu_resets(unsigned nodeid) pci_write_config32(device, HT_INIT_CONTROL, htic); } -static void set_bios_reset(void) +void __attribute__ ((weak)) set_bios_reset(void); +void __attribute__ ((weak)) set_bios_reset(void) { u32 htic; htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); |