summaryrefslogtreecommitdiff
path: root/src/northbridge/amd
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-29 01:34:08 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-05-01 00:49:40 +0200
commit263c679075816a0db146ff5fa6b94689837ff696 (patch)
tree3ac008f38f414e8b6fd79c9bedc75f12318536de /src/northbridge/amd
parent7f731f8d4f0d4dbc109869032f4e993995eac045 (diff)
downloadcoreboot-263c679075816a0db146ff5fa6b94689837ff696.tar.xz
nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14542 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index f0ee6afedd..77ae4838cc 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1439,6 +1439,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
/* Back up the Nibble 0 delays for later use */
memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay));
}
+
+ /* Exit nibble training if current DIMM is not x4 */
+ if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0)
+ break;
}
if (_2Ranks) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index c6ec9052fc..ffc6fb2df0 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -184,6 +184,10 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
}
pDCTData->WLCriticalGrossDelayPrevPass = 0x0;
+
+ /* Exit nibble training if current DIMM is not x4 */
+ if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0)
+ break;
}
return 0;