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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-09 18:55:58 +0200
committerMartin Roth <martinroth@google.com>2018-08-10 21:25:53 +0000
commit3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch)
tree7b5096ca1f81fecf70418020aba184e446f995e0 /src/northbridge/amd
parent1895838e7a3807a6fce324f0dfed193a3821f6df (diff)
downloadcoreboot-3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d.tar.xz
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdfam10/misc_control.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mctecc_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c2
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c2
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c4
6 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index 028f6af460..8323c1e20f 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -19,7 +19,7 @@
/* Turn off machine check triggers when reading
* pci space where there are no devices.
- * This is necessary when scaning the bus for
+ * This is necessary when scanning the bus for
* devices which is done by the kernel
*/
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 18774ebe7a..7be63533a9 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -68,7 +68,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
* (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the
* scrubber is used in two steps. First, the Dram Limit for the node is adjusted
* down to the bottom of the gap, and that ECC dram is initialized. Second, the
- * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is
+ * original Limit is restored, the Scrub base is set to 4GB, and scrubber is
* allowed to run until the Scrub Addr wraps around to zero.
*/
u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 31c23b9445..20a636e480 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -83,7 +83,7 @@ static uint8_t is_fam15h(void)
* (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the
* scrubber is used in two steps. First, the Dram Limit for the node is adjusted
* down to the bottom of the gap, and that ECC dram is initialized. Second, the
- * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is
+ * original Limit is restored, the Scrub base is set to 4GB, and scrubber is
* allowed to run until the Scrub Addr wraps around to zero.
*/
u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index ed942eaff2..f62aa1568a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -924,7 +924,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
u8 WrLvOdt1 = 0;
if (is_fam15h()) {
- /* On Family15h processors, the value for the specific CS being targetted
+ /* On Family15h processors, the value for the specific CS being targeted
* is taken from F2x238 / F2x23C as appropriate, then loaded into F2x9C_x0000_0008
*/
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 3d9ff3ec14..bcf3ddc7fd 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -170,7 +170,7 @@ u16 mctGet_NVbits(u8 index)
case NV_SPDCHK_RESTRT:
val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */
//val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */
- //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */
+ //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node initialization */
if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS)
val = nvram & 0x3;
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 6c2efb320c..c7db156ceb 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -122,7 +122,7 @@ static void SysmemInit(struct gliutable *gl)
int sizembytes, sizebytes;
/*
- * Figure out how much RAM is in the machine and alocate all to the
+ * Figure out how much RAM is in the machine and allocate all to the
* system. We will adjust for SMM now and Frame Buffer later.
*/
sizembytes = sizeram();
@@ -272,7 +272,7 @@ static void GLPCIInit(void)
* base of 1M and top of around 256M
*/
/* we have to create a page-aligned (4KB page) address for base and top */
- /* So we need a high page aligned addresss (pah) and low page aligned address (pal)
+ /* So we need a high page aligned address (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/
pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);