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authorPatrick Georgi <pgeorgi@chromium.org>2018-05-02 17:44:57 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-05-04 13:58:14 +0000
commitb6616ea636e8343a917f575441e5b5d00a0995df (patch)
tree4b1b5f8cef8c385011f144c252a281b5a069a9a3 /src/northbridge/amd
parent4f5bed5210a82eb5f422b72514f9c123a2234876 (diff)
downloadcoreboot-b6616ea636e8343a917f575441e5b5d00a0995df.tar.xz
amd/mct/ddr3: Correctly configure CsMux67
The existing logic to set up CsMux67 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Commit cf1cb5b2d4f528e7eab55ee9393cf72016bac888 did the same for CsMux45 but missed this one. Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25994 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctproc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index ecdd4a25be..38354a5604 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -58,7 +58,7 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
if (((((f2x80 >> 4) & 0xf) == 0x7) || (((f2x80 >> 4) & 0xf) == 0x9))
&& ((f2x64 & 0x3) == 0x3))
cs_mux_67 = 1;
- else if (((((f2x80 >> 4) & 0xa) == 0x7) || (((f2x80 >> 4) & 0xb) == 0x9))
+ else if (((((f2x80 >> 4) & 0xf) == 0xa) || (((f2x80 >> 4) & 0xf) == 0xb))
&& ((f2x64 & 0x3) > 0x1))
cs_mux_67 = 1;
else