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| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-06-06 11:35:43 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:29:45 +0000 |
| commit | 19cbe03534b955cc3c3e3505e66f852184005140 (patch) | |
| tree | 288a31c206d8264c44cd0b7f2749b697262a27f7 /src/northbridge/amd | |
| parent | 86d8c4279d9446826f3f6578793baa5eb2156783 (diff) | |
| download | coreboot-19cbe03534b955cc3c3e3505e66f852184005140.tar.xz | |
nb/amd/amdmct/mct_ddr3: Remove duplicate conditional
This check is already performed at the beginning of
dct_ddr_voltage_index().
Change-Id: Ia73025333c152f14249afb16d05f66791e69e7cb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1347322, 1347323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 945ae8274b..fa8c71447b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3071,11 +3071,6 @@ void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, */ uint8_t dimm_event_l_pin_support = 0; - if (pDCTstat->DIMMValidDCT[dct] == 0) - ddr_voltage_index = 1; - else - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); - ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); max_dimms_installable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); |