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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-08 18:40:28 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-11 16:57:49 +0100 |
| commit | 50583f0e1f82f6863762c75acf01c26e163bf2da (patch) | |
| tree | 97459f96ba4e455659458b43462b8ff11229f0e1 /src/northbridge/amd | |
| parent | 8eb221deafcdba4311979e09020335b3cc4722f5 (diff) | |
| download | coreboot-50583f0e1f82f6863762c75acf01c26e163bf2da.tar.xz | |
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency
must be calculated prior to DQS position training, however the read
latency calculations use read DQS delay values that have not been
set prior to DQS position training.
Set the read DQS delay values to 1UI (i.e worst case) before calculating
the read latency prior to DQS position training.
Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13995
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 8d7ff27105..a66174e68f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1670,9 +1670,11 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t lane; uint32_t dword; uint32_t rx_en_offset; + uint8_t internal_lane; uint8_t dct_training_success; uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; + uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; uint8_t lane_training_success[MAX_BYTE_LANES]; uint8_t dqs_results_array[1024]; @@ -1761,6 +1763,11 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 (4 A) */ write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); + /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ + for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) + current_read_dqs_delay[internal_lane] = 0x20 << 1; + write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); + /* Calculate and program MaxRdLatency */ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); |