Remove leftover AMD CIMX RD890 northbridge support

Change-Id: I3f2cea79a11a52e94f479b25f22eb3726af38fa3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

10 files changed, 0 insertions, 952 deletions

diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig
deleted file mode 100644
index d37418088a..0000000000
--- a/src/northbridge/amd/cimx/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-#Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config AMD_NB_CIMX
-	bool
-	default n
-
-source src/northbridge/amd/cimx/rd890/Kconfig
diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc
deleted file mode 100644
index c695108077..0000000000
--- a/src/northbridge/amd/cimx/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-ifeq ($(CONFIG_AMD_NB_CIMX),y)
-
-subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890
-
-endif
diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig
deleted file mode 100644
index a83a34fc38..0000000000
--- a/src/northbridge/amd/cimx/rd890/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config NORTHBRIDGE_AMD_CIMX_RD890
-	bool
-	default n
-	select AMD_NB_CIMX
-
-if NORTHBRIDGE_AMD_CIMX_RD890
-
-config REDIRECT_NBCIMX_TRACE_TO_SERIAL
-	bool "Redirect AMD Northbridge CIMX Trace to serial console"
-	default n
-	help
-	  This Option allows you to redirect the AMD Northbridge CIMX
-	  Trace debug information to the serial console.
-
-	  Warning: Only enable this option when debuging or tracing AMD CIMX code.
-
-endif # NORTHBRIDGE_AMD_CIMX_RD890
diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc
deleted file mode 100644
index 4704876621..0000000000
--- a/src/northbridge/amd/cimx/rd890/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-
-# RD890 Platform Files
-romstage-y += early.c
-
-ramstage-y += late.c
diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h
deleted file mode 100644
index 1a8c40e0cb..0000000000
--- a/src/northbridge/amd/cimx/rd890/NbPlatform.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _NB_PLATFORM_H_
-#define _NB_PLATFORM_H_
-
-#define SERIAL_OUT_SUPPORT //enable serial output
-#define CIMX_DEBUG
-
-#ifdef  CIMX_DEBUG
-#define CIMX_TRACE_SUPPORT
-#define CIMX_ASSERT_SUPPORT
-#endif
-
-#ifdef  CIMX_TRACE_SUPPORT
-	#define CIMX_INIT_TRACE(Arguments)
-	#if IS_ENABLED(CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL)
-		#define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable
-		#define CIMX_TRACE(Argument) do {do_printk Argument;} while (0)
-	#else
-		#define TRACE_DATA(Ptr, Level)
-		#define CIMX_TRACE(Argument)
-	#endif
-#else
-	#define CIMX_TRACE(Argument)
-	#define CIMX_INIT_TRACE(Arguments)
-#endif
-
-#ifdef CIMX_ASSERT_SUPPORT
-	#ifdef ASSERT
-		#undef ASSERT
-		#define ASSERT CIMX_ASSERT
-	#endif
-	#ifdef CIMX_TRACE_SUPPORT
-		#define CIMX_ASSERT(x)  if (!(x)) {\
-			LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \
-			/*__asm {jmp $}; */\
-		}
-	//#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args)
-	#else
-		#define CIMX_ASSERT(x) if (!(x)) {\
-			/*__asm {jmp $}; */\
-		}
-	#endif
-#else
-	#define CIMX_ASSERT(x)
-#endif
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs)
-#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr)
-
-#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
-
-// CIMX configuration parameters
-/*
- * PCIEX_BASE_ADDRESS  - Define PCIE base address
- */
-#ifdef  MOVE_PCIEBAR_TO_F0000000
-#define PCIEX_BASE_ADDRESS           0xF7000000
-#else
-#define PCIEX_BASE_ADDRESS           CONFIG_MMCONF_BASE_ADDRESS
-#endif
-
-
-
-#define CIMX_S3_SAVE 1
-#include "cbtypes.h"
-#include <console/console.h>
-
-#include "amd.h" //cimx typedef
-#include <amdlib.h>
-#include "amdAcpiLib.h"
-#include "amdAcpiMadt.h"
-#include "amdAcpiIvrs.h"
-#include "amdSbLib.h"
-#include "nbPcie.h"
-
-//must put before the nbType.h
-#include "platform_cfg.h" /*platform dependented configuration */
-#include "nbType.h"
-
-#include "nbLib.h"
-#include "nbDef.h"
-#include "nbInit.h"
-#include "nbHtInit.h"
-#include "nbIommu.h"
-#include "nbEventLog.h"
-#include "nbRegisters.h"
-#include "nbPcieAspm.h"
-#include "nbPcieLinkWidth.h"
-#include "nbPcieHotplug.h"
-#include "nbPciePortRemap.h"
-#include "nbPcieWorkarounds.h"
-#include "nbPcieCplBuffers.h"
-#include "nbPciePllControl.h"
-#include "nbMiscInit.h"
-#include "nbIoApic.h"
-#include "nbPcieSb.h"
-#include "nbRecovery.h"
-#include "nbMaskedMemoryInit.h"
-
-
-#define FIX_PTR_ADDR(x, y) x
-
-#define TRACE_ALWAYS  0xffffffff
-
-#define AmdNbDispatcher NULL
-
-#define CIMX_TRACE_ALL    0xFFFFFFFF
-#define CIMX_NBPOR_TRACE  0xFFFFFFFF
-#define CIMX_NBHT_TRACE   0xFFFFFFFF
-#define CIMX_NBPCIE_TRACE 0xFFFFFFFF
-#define CIMX_NB_TRACE     0xFFFFFFFF
-#define CIMX_NBPCIE_MISC  0xFFFFFFFF
-
-#endif
diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h
deleted file mode 100644
index 898966df6c..0000000000
--- a/src/northbridge/amd/cimx/rd890/amd.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-#include "cbtypes.h"
-
-#define VOLATILE  volatile
-#define CALLCONV
-#define ROMDATA
-#define CIMXAPI   EFIAPI
-
-//
-//
-// AGESA Types and Definitions
-//
-//
-#include <stddef.h>
-
-#define LAST_ENTRY 0xFFFFFFFF
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-#define IN
-#define OUT
-#define IMAGE_SIGNATURE 'DMA$'
-
-typedef UINT32 AGESA_STATUS;
-
-
-#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
-#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
-#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
-#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
-#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
-#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
-#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
-
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
-  PreMemHeap = 0,                                           ///< Create heap in cache.
-  PostMemDram,                                              ///< Create heap in memory.
-  ByHost                                                    ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
-  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
-  AccessWidth16,                                            ///< Access width is 16 bits.
-  AccessWidth32,                                            ///< Access width is 32 bits.
-  AccessWidth64,                                            ///< Access width is 64 bits.
-
-  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
-  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
-  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
-  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-
-// AGESA Structures
-/// The standard header AMD NB UEFI drivers
-typedef struct _AMD_CONFIG_PARAMS {
-  VOID            **PeiServices;              ///< Pointer to PEI service table
-  VOID            *StallPpi;                  ///< Pointer to Stall PPI
-//  UINT32          Func;
-  VOID            *PcieBasePtr;               ///< TBD
-  CALLOUT_ENTRY   CalloutPtr;                 ///<pointer to local driver callback function
-  CALLOUT_ENTRY   InterfaceCalloutPtr;        ///<pointer to external interface driver callback function
-} AMD_CONFIG_PARAMS;
-
-
-/// AGESA Binary module header structure
-typedef struct _AMD_IMAGE_HEADER {
-  IN  UINT32  Signature;                          ///< Binary Signature
-  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
-  IN  CHAR8   Version[12];                        ///< 12 characters version
-  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
-  IN  UINT32  EntryPointAddress;                  ///< Entry address
-  IN  UINT32  ImageBase;                          ///< Image base
-  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
-  IN  UINT32  ImageSize;                          ///< Size
-  IN  UINT16  Checksum;                           ///< Checksum
-  IN  UINT8   ImageType;                          ///< Type
-  IN  UINT8   V_Reserved;                         ///< Reserved
-} AMD_IMAGE_HEADER;
-
-
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
-  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
-  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
-  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
-  IN  MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
-  IN  struct _AMD_MODULE_HEADER  *NextBlockPtr;   ///< Next module header link
-} AMD_MODULE_HEADER;
-
-/// Extended PCI address format
-typedef struct {
-  IN OUT  UINT32      Register:12;                ///< Register offset
-  IN OUT  UINT32      Function:3;                 ///< Function number
-  IN OUT  UINT32      Device:5;                   ///< Device number
-  IN OUT  UINT32      Bus:8;                      ///< Bus number
-  IN OUT  UINT32      Segment:4;                  ///< Segment
-} EXT_PCI_ADDR;
-
-/// Union type for PCI address
-typedef union _PCI_ADDR {
-  IN  UINT32          AddressValue;               ///< Formal address
-  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
-} PCI_ADDR;
-
-#define FUNC_0    0   // bit-placed for PCI address creation
-#define FUNC_1    1
-#define FUNC_2    2
-#define FUNC_3    3
-#define FUNC_4    4
-#define FUNC_5    5
-#define FUNC_6    6
-#define FUNC_7    7
-
-//   SBDFO - Segment Bus Device Function Offset
-//   31:28   Segment (4-bits)
-//   27:20   Bus     (8-bits)
-//   19:15   Device  (5-bits)
-//   14:12   Function(3-bits)
-//   11:00   Offset  (12-bits)
-
-#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
-                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/// CPUID data received registers format
-typedef struct _CPUID_DATA {
-  IN  OUT UINT32          EAX_Reg;                ///< CPUID instruction result in EAX
-  IN  OUT UINT32          EBX_Reg;                ///< CPUID instruction result in EBX
-  IN  OUT UINT32          ECX_Reg;                ///< CPUID instruction result in ECX
-  IN  OUT UINT32          EDX_Reg;                ///< CPUID instruction result in EDX
-} CPUID_DATA;
-
-#define WARM_RESET 1
-#define COLD_RESET 2
-
-/// HT frequency for external callbacks
-typedef enum {
-  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
-  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
-  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
-  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
-  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
-  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
-  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
-  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
-  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
-  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
-  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
-  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
-  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
-  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
-  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
-  HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
-} HT_FREQUENCIES;
-
-#ifndef BIT0
-  #define BIT0        0x0000000000000001ull
-#endif
-#ifndef BIT1
-  #define BIT1        0x0000000000000002ull
-#endif
-#ifndef BIT2
-  #define BIT2        0x0000000000000004ull
-#endif
-#ifndef BIT3
-  #define BIT3        0x0000000000000008ull
-#endif
-#ifndef BIT4
-  #define BIT4        0x0000000000000010ull
-#endif
-#ifndef BIT5
-  #define BIT5        0x0000000000000020ull
-#endif
-#ifndef BIT6
-  #define BIT6        0x0000000000000040ull
-#endif
-#ifndef BIT7
-  #define BIT7        0x0000000000000080ull
-#endif
-#ifndef BIT8
-  #define BIT8        0x0000000000000100ull
-#endif
-#ifndef BIT9
-  #define BIT9        0x0000000000000200ull
-#endif
-#ifndef BIT10
-  #define BIT10       0x0000000000000400ull
-#endif
-#ifndef BIT11
-  #define BIT11       0x0000000000000800ull
-#endif
-#ifndef BIT12
-  #define BIT12       0x0000000000001000ull
-#endif
-#ifndef BIT13
-  #define BIT13       0x0000000000002000ull
-#endif
-#ifndef BIT14
-  #define BIT14       0x0000000000004000ull
-#endif
-#ifndef BIT15
-  #define BIT15       0x0000000000008000ull
-#endif
-#ifndef BIT16
-  #define BIT16       0x0000000000010000ull
-#endif
-#ifndef BIT17
-  #define BIT17       0x0000000000020000ull
-#endif
-#ifndef BIT18
-  #define BIT18       0x0000000000040000ull
-#endif
-#ifndef BIT19
-  #define BIT19       0x0000000000080000ull
-#endif
-#ifndef BIT20
-  #define BIT20       0x0000000000100000ull
-#endif
-#ifndef BIT21
-  #define BIT21       0x0000000000200000ull
-#endif
-#ifndef BIT22
-  #define BIT22       0x0000000000400000ull
-#endif
-#ifndef BIT23
-  #define BIT23       0x0000000000800000ull
-#endif
-#ifndef BIT24
-  #define BIT24       0x0000000001000000ull
-#endif
-#ifndef BIT25
-  #define BIT25       0x0000000002000000ull
-#endif
-#ifndef BIT26
-  #define BIT26       0x0000000004000000ull
-#endif
-#ifndef BIT27
-  #define BIT27       0x0000000008000000ull
-#endif
-#ifndef BIT28
-  #define BIT28       0x0000000010000000ull
-#endif
-#ifndef BIT29
-  #define BIT29       0x0000000020000000ull
-#endif
-#ifndef BIT30
-  #define BIT30       0x0000000040000000ull
-#endif
-#ifndef BIT31
-  #define BIT31       0x0000000080000000ull
-#endif
-#ifndef BIT32
-  #define BIT32       0x0000000100000000ull
-#endif
-#ifndef BIT33
-  #define BIT33       0x0000000200000000ull
-#endif
-#ifndef BIT34
-  #define BIT34       0x0000000400000000ull
-#endif
-#ifndef BIT35
-  #define BIT35       0x0000000800000000ull
-#endif
-#ifndef BIT36
-  #define BIT36       0x0000001000000000ull
-#endif
-#ifndef BIT37
-  #define BIT37       0x0000002000000000ull
-#endif
-#ifndef BIT38
-  #define BIT38       0x0000004000000000ull
-#endif
-#ifndef BIT39
-  #define BIT39       0x0000008000000000ull
-#endif
-#ifndef BIT40
-  #define BIT40       0x0000010000000000ull
-#endif
-#ifndef BIT41
-  #define BIT41       0x0000020000000000ull
-#endif
-#ifndef BIT42
-  #define BIT42       0x0000040000000000ull
-#endif
-#ifndef BIT43
-  #define BIT43       0x0000080000000000ull
-#endif
-#ifndef BIT44
-  #define BIT44       0x0000100000000000ull
-#endif
-#ifndef BIT45
-  #define BIT45       0x0000200000000000ull
-#endif
-#ifndef BIT46
-  #define BIT46       0x0000400000000000ull
-#endif
-#ifndef BIT47
-  #define BIT47       0x0000800000000000ull
-#endif
-#ifndef BIT48
-  #define BIT48       0x0001000000000000ull
-#endif
-#ifndef BIT49
-  #define BIT49       0x0002000000000000ull
-#endif
-#ifndef BIT50
-  #define BIT50       0x0004000000000000ull
-#endif
-#ifndef BIT51
-  #define BIT51       0x0008000000000000ull
-#endif
-#ifndef BIT52
-  #define BIT52       0x0010000000000000ull
-#endif
-#ifndef BIT53
-  #define BIT53       0x0020000000000000ull
-#endif
-#ifndef BIT54
-  #define BIT54       0x0040000000000000ull
-#endif
-#ifndef BIT55
-  #define BIT55       0x0080000000000000ull
-#endif
-#ifndef BIT56
-  #define BIT56       0x0100000000000000ull
-#endif
-#ifndef BIT57
-  #define BIT57       0x0200000000000000ull
-#endif
-#ifndef BIT58
-  #define BIT58       0x0400000000000000ull
-#endif
-#ifndef BIT59
-  #define BIT59       0x0800000000000000ull
-#endif
-#ifndef BIT60
-  #define BIT60       0x1000000000000000ull
-#endif
-#ifndef BIT61
-  #define BIT61       0x2000000000000000ull
-#endif
-#ifndef BIT62
-  #define BIT62       0x4000000000000000ull
-#endif
-#ifndef BIT63
-  #define BIT63       0x8000000000000000ull
-#endif
-
-#ifdef  ASSERT
-  #undef  ASSERT
-  #define ASSERT(x)
-#endif
-
-#endif
diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h
deleted file mode 100644
index 4b2edccc39..0000000000
--- a/src/northbridge/amd/cimx/rd890/chip.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CIMX_RD890_CHIP_H_
-#define _CIMX_RD890_CHIP_H_
-
-/**
- * RD890 specific device configuration
- */
-struct northbridge_amd_cimx_rd890_config
-{
-	u8 gpp1_configuration;
-	u8 gpp2_configuration;
-	u8 gpp3a_configuration;
-	u16 port_enable;
-};
-
-#endif /* _CIMX_RD890_CHIP_H_ */
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c
deleted file mode 100644
index 4904e5258e..0000000000
--- a/src/northbridge/amd/cimx/rd890/early.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include "NbPlatform.h"
-#include "rd890_cfg.h"
-#include "nb_cimx.h"
-
-
-/**
- * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
- *
- * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
- * Disable all Pcie Bridges to work around It.
- */
-void sr56x0_rd890_disable_pcie_bridge(void)
-{
-	u32			nb_dev;
-	u32			mask;
-	u32			val;
-	AMD_NB_CONFIG_BLOCK	cfg_block;
-	AMD_NB_CONFIG_BLOCK	*cfg_ptr = &cfg_block;
-	AMD_NB_CONFIG		*nb_cfg  = &(cfg_block.Northbridges[0]);
-
-	nb_cfg->ConfigPtr = &cfg_ptr;
-	nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-	val = (1 << 2) | (1 << 3); /*GPP1*/
-	val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
-	val |= (1 << 18) | (1 << 19); /*GPP2*/
-	val |= (1 << 20); /*GPP3b*/
-	mask = ~val;
-	LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C,
-			AccessS3SaveWidth32,
-			mask,
-			val,
-			nb_cfg);
-}
-
-
-/**
- * @brief South Bridge CIMx romstage entry,
- *  wrapper of AmdPowerOnResetInit entry point.
- */
-void nb_Poweron_Init(void)
-{
-	NB_CONFIG nb_cfg[MAX_NB_COUNT];
-	HT_CONFIG ht_cfg[MAX_NB_COUNT];
-	PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
-	AMD_NB_CONFIG_BLOCK gConfig;
-	AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig;
-	AGESA_STATUS status;
-
-	printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__);
-	CIMX_INIT_TRACE();
-	CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n"));
-	rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
-
-	if (ConfigPtr->StandardHeader.CalloutPtr != NULL) {
-		ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig);
-	}
-
-	status = AmdPowerOnResetInit(&gConfig);
-	printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status);
-}
-
-/**
- * @brief South Bridge CIMx romstage entry,
- *  wrapper of AmdHtInit entry point.
- */
-void nb_Ht_Init(void)
-{
-	AGESA_STATUS status;
-	NB_CONFIG nb_cfg[MAX_NB_COUNT];
-	HT_CONFIG ht_cfg[MAX_NB_COUNT];
-	PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
-	AMD_NB_CONFIG_BLOCK gConfig;
-	AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig;
-	u32 i;
-
-	rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
-
-	//Initialize HT structure
-	LibSystemApiCall(AmdHtInitializer, &gConfig);
-	for (i = 0; i < MAX_NB_COUNT; i ++) {
-		if (ConfigPtr->StandardHeader.CalloutPtr != NULL) {
-			ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i]));
-		}
-	}
-
-	status = LibSystemApiCall(AmdHtInit, &gConfig);
-	printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status);
-}
-
-void nb_S3_Init(void)
-{
-	//TODO
-}
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
deleted file mode 100644
index 9581527a44..0000000000
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "NbPlatform.h"
-#include "nb_cimx.h"
-#include "rd890_cfg.h"
-
-
-/**
- * Global RD890 CIMX Configuration structure
- */
-static NB_CONFIG nb_cfg[MAX_NB_COUNT];
-static HT_CONFIG ht_cfg[MAX_NB_COUNT];
-static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
-static AMD_NB_CONFIG_BLOCK gConfig;
-
-
-/**
- * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
- * After this call EP are fully operational on particular NB
- */
-void nb_Pcie_Early_Init(void)
-{
-	LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig);
-}
-
-void nb_Pcie_Late_Init(void)
-{
-	LibSystemApiCall(AmdPcieLateInit, &gConfig);
-}
-
-void nb_Early_Post_Init(void)
-{
-	LibSystemApiCall(AmdEarlyPostInit, &gConfig);
-}
-
-void nb_Mid_Post_Init(void)
-{
-	LibSystemApiCall(AmdMidPostInit, &gConfig);
-}
-
-void nb_Late_Post_Init(void)
-{
-	LibSystemApiCall(AmdLatePostInit, &gConfig);
-}
-
-static void rd890_enable(device_t dev)
-{
-	u32 address = 0;
-	u32 devfn;
-	AMD_NB_CONFIG *NbConfigPtr = NULL;
-
-	u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */
-	address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
-	NbConfigPtr = &(gConfig.Northbridges[nb_index]);
-
-	devfn = dev->path.pci.devfn;
-	printk(BIOS_INFO, "rd890_enable  ");
-	printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n",
-			0, (devfn >> 3), (devfn & 0x07), dev->enabled);
-
-	/* we only do this once */
-	if (devfn == 0) {
-		/* CIMX configuration defualt initialize */
-		rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
-		if (gConfig.StandardHeader.CalloutPtr != NULL) {
-			gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig,
-					(uintptr_t)dev, (VOID*)NbConfigPtr);
-		}
-		/* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
-		 * After this call EP are fully operational on particular NB
-		 */
-		nb_Pcie_Early_Init();
-
-		if (gConfig.StandardHeader.CalloutPtr != NULL) {
-			gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr);
-		}
-		nb_Early_Post_Init();
-
-		if (gConfig.StandardHeader.CalloutPtr != NULL) {
-			gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr);
-		}
-		nb_Mid_Post_Init();
-		nb_Pcie_Late_Init();
-
-		if (gConfig.StandardHeader.CalloutPtr != NULL) {
-			gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr);
-		}
-		nb_Late_Post_Init();
-	}
-}
-
-struct chip_operations northbridge_amd_cimx_rd890_ops = {
-	CHIP_NAME("ATI rd890")
-	.enable_dev = rd890_enable,
-};
-
-
-static void ioapic_init(struct device *dev)
-{
-	void *ioapic_base;
-
-	pci_write_config32(dev, 0xF8, 0x1);
-	ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
-	clear_ioapic(ioapic_base);
-	setup_ioapic(ioapic_base, 1);
-}
-
-static void rd890_read_resource(struct device *dev)
-{
-	pci_dev_read_resources(dev);
-
-	/* rpr6.2.(1). Write the Base Address Register (BAR) */
-	pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
-	pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
-
-	compact_resources(dev);
-}
-
-/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
-static void rd890_set_resources(struct device *dev)
-{
-	pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
-	pci_dev_set_resources(dev);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = pci_dev_set_subsystem,
-};
-
-static struct device_operations ht_ops = {
-	.read_resources = rd890_read_resource,
-	.set_resources = rd890_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = ioapic_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const unsigned short driver_ids[] = {
-	PCI_DEVICE_ID_AMD_SR5690_HT,
-	PCI_DEVICE_ID_AMD_SR5670_HT,
-	PCI_DEVICE_ID_AMD_SR5650_HT,
-	PCI_DEVICE_ID_AMD_RD890TV_HT,
-	PCI_DEVICE_ID_AMD_RD890_HT,
-	PCI_DEVICE_ID_AMD_990FX_HT,
-	0
-};
-
-static const struct pci_driver ht_driver_sr5690 __pci_driver = {
-	.ops = &ht_ops,
-	.vendor = PCI_VENDOR_ID_ATI,
-	.devices= driver_ids,
-};
diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h
deleted file mode 100644
index 24f38db771..0000000000
--- a/src/northbridge/amd/cimx/rd890/nb_cimx.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _NB_CIMX_H_
-#define _NB_CIMX_H_
-
-/**
- * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
- *
- * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
- * Disable all Pcie Bridges to work around It.
- */
-void sr56x0_rd890_disable_pcie_bridge(void);
-
-/**
- * Northbridge CIMX entries point
- */
-void nb_Poweron_Init(void);
-void nb_Ht_Init(void);
-void nb_S3_Init(void);
-void nb_Early_Post_Init(void);
-void nb_Mid_Post_Init(void);
-void nb_Late_Post_Init(void);
-void nb_Pcie_Early_Init(void);
-void nb_Pcie_Late_Init(void);
-
-#endif /* _NB_CIMX_H_ */