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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-12-31 12:56:53 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2009-12-31 12:56:53 +0000
commit1bb68289001f95b49499ac8eb483a7a10e64cc52 (patch)
treec1d60ba92227bc29ef48c0afb273db4825524dd2 /src/northbridge/amd
parent9db833bec394b886ca990965970cdb100b65d9ac (diff)
downloadcoreboot-1bb68289001f95b49499ac8eb483a7a10e64cc52.tar.xz
romcc:
- Set __PRE_RAM__ define per default - Properly handle ignored (#ifdef'd out) #include lines amd/serengeti_cheetah_fam10: - write ACPI files to $(obj) instead of the top dir (alias $(CURDIR)) tinybootblock: - provide a way to define code that should be added to the bootblock, to map the entire ROM for use by CBFS amd/model_fxx, amd/model_10xxx: - add CONFIG_SSE walkcbfs.S: - eliminate the use of two registers, to make space for romcc to wiggle amd/serengeti_cheetah_fam10: - use the enable_rom framework. not entirely functional yet Boot-tested on emulation/qemu-x86 Build-tested on amd/serengeti_cheetah_fam10 amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdfam10/Kconfig5
-rw-r--r--src/northbridge/amd/amdfam10/Makefile.inc36
-rw-r--r--src/northbridge/amd/amdfam10/bootblock.c12
3 files changed, 35 insertions, 18 deletions
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index aa344c646e..daff00a0d4 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -52,4 +52,9 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
default n
depends on NORTHBRIDGE_AMD_AMDFAM10
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/amd/amdfam10/bootblock.c"
+ depends on NORTHBRIDGE_AMD_AMDFAM10
+
source src/northbridge/amd/amdfam10/root_complex/Kconfig
diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc
index bcc7cab3d3..6f4c6b3ac9 100644
--- a/src/northbridge/amd/amdfam10/Makefile.inc
+++ b/src/northbridge/amd/amdfam10/Makefile.inc
@@ -13,33 +13,33 @@ obj-y += get_pci1234.o
ifdef POST_EVALUATION
$(obj)/northbridge/amd/amdfam10/ssdt.c: $(src)/northbridge/amd/amdfam10/ssdt.dsl
- iasl -p $(CURDIR)/ssdt -tc $<
- perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex
- mv ssdt.hex $@
+ iasl -p $(obj)/ssdt -tc $<
+ perl -pi -e 's/AmlCode/AmlCode_ssdt/g' $(obj)/ssdt.hex
+ mv $(obj)/ssdt.hex $@
$(obj)/northbridge/amd/amdfam10/sspr1.c: $(src)/northbridge/amd/amdfam10/sspr1.dsl
- iasl -p $(CURDIR)/sspr1 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex
- mv sspr1.hex $@
+ iasl -p $(obj)/sspr1 -tc $<
+ perl -pi -e 's/AmlCode/AmlCode_sspr1/g' $(obj)/sspr1.hex
+ mv $(obj)/sspr1.hex $@
$(obj)/northbridge/amd/amdfam10/sspr2.c: $(src)/northbridge/amd/amdfam10/sspr2.dsl
- iasl -p $(CURDIR)/sspr2 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex
- mv sspr2.hex $@
+ iasl -p $(obj)/sspr2 -tc $<
+ perl -pi -e 's/AmlCode/AmlCode_sspr2/g' $(obj)/sspr2.hex
+ mv $(obj)/sspr2.hex $@
$(obj)/northbridge/amd/amdfam10/sspr3.c: $(src)/northbridge/amd/amdfam10/sspr3.dsl
- iasl -p $(CURDIR)/sspr3 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex
- mv sspr3.hex $@
+ iasl -p $(obj)/sspr3 -tc $<
+ perl -pi -e 's/AmlCode/AmlCode_sspr3/g' $(obj)/sspr3.hex
+ mv $(obj)/sspr3.hex $@
$(obj)/northbridge/amd/amdfam10/sspr4.c: $(src)/northbridge/amd/amdfam10/sspr4.dsl
- iasl -p $(CURDIR)/sspr4 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex
- mv sspr4.hex $@
+ iasl -p $(obj)/sspr4 -tc $<
+ perl -pi -e 's/AmlCode/AmlCode_sspr4/g' $(obj)/sspr4.hex
+ mv $(obj)/sspr4.hex $@
$(obj)/northbridge/amd/amdfam10/sspr5.c: $(src)/northbridge/amd/amdfam10/sspr5.dsl
- iasl -p $(CURDIR)/sspr5 -tc $<
- perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex
- mv sspr5.hex $@
+ iasl -p $(obj)/sspr5 -tc $<
+ perl -pi -e 's/AmlCode/AmlCode_sspr5/g' $(obj)/sspr5.hex
+ mv $(obj)/sspr5.hex $@
endif
diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
new file mode 100644
index 0000000000..612004a7eb
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -0,0 +1,12 @@
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include "northbridge/amd/amdfam10/early_ht.c"
+
+static void bootblock_northbridge_init(void) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ /* mov bsp to bus 0xff when > 8 nodes */
+ set_bsp_node_CHtExtNodeCfgEn();
+ enumerate_ht_chain();
+}