cpu/amd/geode_lx: Drop support

These chips are still using LATE_CBMEM which was agreed upon to
be removed after release 4.7. It is now more than 1 year later
and they still linger around.

The work and review to bring this code up to date can happen on
the 4.9 branch and then squashed together and merged back into
mainline when done.

Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>

10 files changed, 0 insertions, 2295 deletions

diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig
deleted file mode 100644
index 53a0e0556b..0000000000
--- a/src/northbridge/amd/lx/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-config NORTHBRIDGE_AMD_LX
-	bool
-	select GEODE_VSA
-	select LATE_CBMEM_INIT
-	select NO_RELOCATABLE_RAMSTAGE
-
-if NORTHBRIDGE_AMD_LX
-
-config VIDEO_MB
-	int
-	default 8
-
-config PLL_MANUAL_CONFIG
-	bool
-
-if PLL_MANUAL_CONFIG
-
-# "Core/GLIU Frequency"
-config CORE_GLIU_500_266
-	bool # "500MHz / 266MHz"
-
-config CORE_GLIU_500_333
-	bool # "500MHz / 333MHz"
-
-config CORE_GLIU_500_400
-	bool # "500MHz / 400MHz"
-
-config PLLMSRhi
-	hex
-	default 0x39c if CORE_GLIU_500_266
-	default 0x49c if CORE_GLIU_500_333
-	default 0x59c if CORE_GLIU_500_400
-
-config PLLMSRlo
-	hex
-
-endif
-
-endif
diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc
deleted file mode 100644
index e36139ff6d..0000000000
--- a/src/northbridge/amd/lx/Makefile.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-ifeq ($(CONFIG_NORTHBRIDGE_AMD_LX),y)
-
-ramstage-y += northbridge.c
-ramstage-y += northbridgeinit.c
-ramstage-y += grphinit.c
-
-romstage-y += raminit.c
-romstage-y += generic_sdram.c
-romstage-y += pll_reset.c
-
-endif
diff --git a/src/northbridge/amd/lx/generic_sdram.c b/src/northbridge/amd/lx/generic_sdram.c
deleted file mode 100644
index e0869cdbca..0000000000
--- a/src/northbridge/amd/lx/generic_sdram.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <northbridge/amd/lx/raminit.h>
-
-/* Setup SDRAM */
-void sdram_initialize(int controllers, const struct mem_controller *ctrl)
-{
-	int i;
-	/* Set the registers we can set once to reasonable values */
-	for (i = 0; i < controllers; i++) {
-		printk(BIOS_DEBUG, "Ram1.%02x\n", i);
-		sdram_set_registers(ctrl + i);
-	}
-
-	/* Now setup those things we can auto detect */
-	for (i = 0; i < controllers; i++) {
-		printk(BIOS_DEBUG, "Ram2.%02x\n", i);
-		sdram_set_spd_registers(ctrl + i);
-	}
-
-	/* Now that everything is setup enable the SDRAM.
-	 * Some chipsets do the work for us while on others
-	 * we need to it by hand.
-	 */
-	printk(BIOS_DEBUG, "Ram3\n");
-
-	sdram_enable(controllers, ctrl);
-
-	printk(BIOS_DEBUG, "Ram4\n");
-}
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
deleted file mode 100644
index 1adb9af7c1..0000000000
--- a/src/northbridge/amd/lx/grphinit.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <stdint.h>
-#include <cpu/amd/vr.h>
-#include <console/console.h>
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <stdlib.h>
-
-void geodelx_vga_msr_init(void);
-void graphics_init(void);
-
-struct msrinit {
-	u32 msrnum;
-	msr_t msr;
-};
-
-static const struct msrinit geodelx_vga_msr[] = {
-	/* Enable the GLIU Memory routing to the hardware
-	* PDID1 : Port 4, GLIU0
-	* PBASE : 0x000A0
-	* PMASK : 0xFFFE0
-	*/
-	{.msrnum = MSR_GLIU0_BASE4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},
-	/* Enable the GLIU IO Routing
-	* IDID  : Port 4, GLIU0
-	* IBASE : 0x003c0
-	* IMASK : 0xffff0
-	*/
-	{.msrnum = GLIU0_IOD_BM_0,  {.lo = 0x3c0ffff0, .hi = 0x80000000}},
-	/* Enable the GLIU IO Routing
-	* IDID  : Port 4, GLIU0
-	* IBASE : 0x003d0
-	* IMASK : 0xffff0
-	*/
-	{.msrnum = GLIU0_IOD_BM_1,  {.lo = 0x3d0ffff0, .hi = 0x80000000}},
-};
-
-void geodelx_vga_msr_init(void)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(geodelx_vga_msr); i++)
-		wrmsr(geodelx_vga_msr[i].msrnum, geodelx_vga_msr[i].msr);
-}
-
- /*
-  * This function mirrors the Graphics_Init routine in GeodeROM.
-  */
-void graphics_init(void)
-{
-	uint16_t wClassIndex, wData, res;
-
-	/* SoftVG initialization */
-	printk(BIOS_DEBUG, "Graphics init...\n");
-
-	geodelx_vga_msr_init();
-
-	/* Call SoftVG with the main configuration parameters. */
-	/* NOTE: SoftVG expects the memory size to be given in 2MB blocks */
-
-	wClassIndex = (VRC_VG << 8) + VG_CONFIG;
-
-	/*
-	 * Graphics Driver Enabled (13)                         0, NO (lets BIOS controls the GP)
-	 * External Monochrome Card Support(12)         0, NO
-	 * Controller Priority Select(11)                       1, Primary
-	 * Display Select(10:8)                                         0x0, CRT
-	 * Graphics Memory Size(7:1)                            CONFIG_VIDEO_MB >> 1,
-	 *                                                                                      defined in devicetree.cb
-	 * PLL Reference Clock Bypass(0)                        0, Default
-	 */
-
-	/* Video RAM has to be given in 2MB chunks
-	 *   the value is read @ 7:1 (value in 7:0 looks like /2)
-	 *   so we can add the real value in megabytes
-	 */
-
-	wData = VG_CFG_DRIVER | VG_CFG_PRIORITY |
-			VG_CFG_DSCRT | (CONFIG_VIDEO_MB & VG_MEM_MASK);
-	vrWrite(wClassIndex, wData);
-
-	res = vrRead(wClassIndex);
-	printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
-}
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
deleted file mode 100644
index ffaaa19ca3..0000000000
--- a/src/northbridge/amd/lx/northbridge.c
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdlib.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/vr.h>
-#include "northbridge.h"
-#include <southbridge/amd/cs5536/cs5536.h>
-
-
-/* here is programming for the various MSRs.*/
-#define IM_QWAIT 0x100000
-
-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */	/* in high */
-#define DMCF_SERIAL_LOAD_MISSES  (2)	/* enabled */
-
-/* these are the 8-bit attributes for controlling RCONF registers */
-#define CACHE_DISABLE (1<<0)
-#define WRITE_ALLOCATE (1<<1)
-#define WRITE_PROTECT (1<<2)
-#define WRITE_THROUGH (1<<3)
-#define WRITE_COMBINE (1<<4)
-#define WRITE_SERIALIZE (1<<5)
-
-/* RAM has none of this stuff */
-#define RAM_PROPERTIES (0)
-#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
-#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
-#define MSR_WS_CD_DEFAULT (0x21212121)
-
-/* 1810-1817 give you 8 registers with which to program protection regions */
-/* the are region configuration range registers, or RRCF */
-/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
-/* so no left-shift needed for top or base */
-#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
-#define RRCF_LOW_CD(base)	RRCF_LOW(base, CACHE_DISABLE)
-
-/* build initializer for P2D MSR */
-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
-
-void print_conf(void);
-void graphics_init(void);
-void do_vsmbios(void);
-
-struct msr_defaults {
-	int msr_no;
-	msr_t msr;
-} msr_defaults[] = {
-	{
-		0x1700, {
-	.hi = 0,.lo = IM_QWAIT}}, {
-		0x1800, {
-	.hi = DMCF_WRITE_SERIALIZE_REQUEST,.lo =
-			    DMCF_SERIAL_LOAD_MISSES}},
-	    /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
-	    /* for 180a, for now, we assume VSM will configure it */
-	    /* 180b is left at reset value,a0000-bffff is non-cacheable */
-	    /* 180c, c0000-dffff is set to write serialize and non-cachable */
-	    /* oops, 180c will be set by CPU bug handling in cpubug.c */
-	    //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
-	    /* 180d is left at default, e0000-fffff is non-cached */
-	    /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
-	    /* we will not set 0x180f, the DMM,yet */
-	    //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
-	    //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
-	    //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
-	    //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
-	    /* now for GLPCI routing */
-	    /* GLIU0 */
-	    P2D_BM(MSR_GLIU0_BASE1, 0x1, 0x0, 0x0, 0xfff80),
-	    P2D_BM(MSR_GLIU0_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
-	    P2D_SC(MSR_GLIU0_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
-	    /* GLIU1 */
-	    P2D_BM(MSR_GLIU1_BASE1, 0x1, 0x0, 0x0, 0xfff80),
-	    P2D_BM(MSR_GLIU1_BASE2, 0x1, 0x0, 0x80000, 0xfffe0),
-	    P2D_SC(MSR_GLIU1_SHADOW, 0x1, 0x0, 0x0, 0xff03, 0xC0000), {
-	0}
-};
-
-/* Print the platform configuration - do before PCI init or it will not
- * work right.
- */
-void print_conf(void)
-{
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
-	int i;
-	unsigned long iol;
-	msr_t msr;
-
-	int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
-		CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
-		CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
-		GLCP_DELAY_CONTROLS, GL_END
-	};
-
-	int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
-		MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
-		GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
-		GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
-		MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
-		GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
-		GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
-		GLIU0_GLD_MSR_COH, GL_END
-	};
-
-	int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
-		MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
-		MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
-		MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
-		GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
-		GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
-		GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
-		GLIU1_GLD_MSR_COH, GL_END
-	};
-
-	int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
-		CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
-	};
-
-	int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
-		MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
-		MDD_IRQM_PRIM, GL_END
-	};
-
-	int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
-		GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
-		GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
-	};
-
-	int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
-		MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
-		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
-	};
-
-	printk(BIOS_DEBUG, "---------- CPU ------------\n");
-
-	for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
-		msr = rdmsr(cpu_msr_defs[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-			     cpu_msr_defs[i], msr.hi, msr.lo);
-	}
-
-	printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
-
-	for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
-		msr = rdmsr(gliu0_msr_defs[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-			     gliu0_msr_defs[i], msr.hi, msr.lo);
-	}
-
-	printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
-
-	for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
-		msr = rdmsr(gliu1_msr_defs[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
-			     gliu1_msr_defs[i], msr.hi, msr.lo);
-	}
-
-	printk(BIOS_DEBUG, "---------- RCONF ------------\n");
-
-	for (i = 0; rconf_msr[i] != GL_END; i++) {
-		msr = rdmsr(rconf_msr[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
-			     msr.hi, msr.lo);
-	}
-
-	printk(BIOS_DEBUG, "---------- VARIA ------------\n");
-	msr = rdmsr(0x51300010);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
-		     msr.lo);
-
-	msr = rdmsr(0x51400015);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
-		     msr.lo);
-
-	printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
-	msr = rdmsr(MDD_IRQM_YLOW);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
-		     msr.lo);
-	msr = rdmsr(MDD_IRQM_YHIGH);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
-		     msr.hi, msr.lo);
-	msr = rdmsr(MDD_IRQM_ZLOW);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
-		     msr.lo);
-	msr = rdmsr(MDD_IRQM_ZHIGH);
-	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
-		     msr.hi, msr.lo);
-
-	printk(BIOS_DEBUG, "---------- PCI ------------\n");
-
-	for (i = 0; pci_msr[i] != GL_END; i++) {
-		msr = rdmsr(pci_msr[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
-			     msr.hi, msr.lo);
-	}
-
-	printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
-
-	for (i = 0; dma_msr[i] != GL_END; i++) {
-		msr = rdmsr(dma_msr[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
-			     msr.hi, msr.lo);
-	}
-
-	printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
-
-	for (i = 0; cs5536_msr[i] != GL_END; i++) {
-		msr = rdmsr(cs5536_msr[i]);
-		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
-			     msr.hi, msr.lo);
-	}
-
-	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
-	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
-		     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
-	iol = inl(GPIOL_EVENTS_ENABLE);
-	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
-		     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
-	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
-	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
-		     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
-	iol = inl(GPIO_MAPPER_X);
-	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
-		     iol);
-#endif				//CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
-}
-
-/* todo: add a resource record. We don't do this here because this may be called when
-  * very little of the platform is actually working.
-  */
-int sizeram(void)
-{
-	msr_t msr;
-	int sizem = 0;
-	unsigned short dimm;
-
-	/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
-	msr = rdmsr(MC_CF07_DATA);
-	printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
-
-	/* dimm 0 */
-	dimm = msr.hi;
-	/* installed? */
-	if ((dimm & 7) != 7) {
-		sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
-	}
-
-	/* dimm 1 */
-	dimm = msr.hi >> 16;
-	/* installed? */
-	if ((dimm & 7) != 7) {
-		sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
-	}
-
-	printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
-	return sizem;
-}
-
-static void enable_shadow(struct device *dev)
-{
-}
-
-static void northbridge_init(struct device *dev)
-{
-
-	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
-	enable_shadow(dev);
-
-}
-
-static void northbridge_set_resources(struct device *dev)
-{
-	uint8_t line;
-
-	struct bus *bus;
-	for (bus = dev->link_list; bus; bus = bus->next) {
-		if (bus->children) {
-			printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
-			     bus->secondary);
-			assign_resources(bus);
-		}
-	}
-
-	/* set a default latency timer */
-	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
-
-	/* set a default secondary latency timer */
-	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
-		pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
-	}
-
-	/* zero the irq settings */
-	line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
-	if (line) {
-		pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
-	}
-
-	/* set the cache line size, so far 64 bytes is good for everyone */
-	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
-}
-
-static struct device_operations northbridge_operations = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = northbridge_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = northbridge_init,
-	.enable = 0,
-	.ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
-};
-
-#include <cbmem.h>
-
-static void pci_domain_set_resources(struct device *dev)
-{
-	int idx;
-	u32 tomk;
-	struct device *mc_dev;
-
-	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
-	mc_dev = dev->link_list->children;
-	if (mc_dev) {
-		tomk = restore_top_of_low_cacheable() / 1024;
-		/* Report the memory regions
-		   All memory up to systop except 0xa0000-0xbffff */
-		idx = 10;
-		ram_resource(dev, idx++, 0, 640);
-		ram_resource(dev, idx++, 768, tomk - 768);	// Systop - 0xc0000 -> KB
-
-		set_late_cbmem_top(tomk * 1024);
-	}
-
-	assign_resources(dev->link_list);
-}
-
-static void pci_domain_enable(struct device *dev)
-{
-	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
-	// do this here for now -- this chip really breaks our device model
-	northbridge_init_early();
-	cpubug();
-	chipsetinit();
-
-	do_vsmbios();		// do the magic stuff here, so prepare your tambourine;)
-
-	graphics_init();
-}
-
-static struct device_operations pci_domain_ops = {
-	.read_resources = pci_domain_read_resources,
-	.set_resources = pci_domain_set_resources,
-	.enable_resources = NULL,
-	.scan_bus = pci_domain_scan_bus,
-	.enable = pci_domain_enable,
-};
-
-static void cpu_bus_init(struct device *dev)
-{
-	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
-
-	initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
-	.read_resources = DEVICE_NOOP,
-	.set_resources = DEVICE_NOOP,
-	.enable_resources = DEVICE_NOOP,
-	.init = cpu_bus_init,
-	.scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
-	printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
-		    __func__, dev->path.type);
-
-	/* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN)
-		dev->ops = &pci_domain_ops;
-	else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
-		dev->ops = &cpu_bus_ops;
-}
-
-struct chip_operations northbridge_amd_lx_ops = {
-	CHIP_NAME("AMD LX Northbridge")
-	    .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
deleted file mode 100644
index 51c2c14e75..0000000000
--- a/src/northbridge/amd/lx/northbridge.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_AMD_LX_H
-#define NORTHBRIDGE_AMD_LX_H
-
-/* northbridge.c */
-int sizeram(void);
-
-/* northbridgeinit.c */
-void northbridge_init_early(void);
-
-/* pll_reset.c */
-unsigned int GeodeLinkSpeed(void);
-void lx_pll_reset(void);
-
-void lx_msr_init(void);
-
-#endif
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
deleted file mode 100644
index 9655c0e4e0..0000000000
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ /dev/null
@@ -1,754 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <stdlib.h>
-#include <string.h>
-#include "northbridge.h"
-#include <cpu/amd/lxdef.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/cache.h>
-#include <cbmem.h>
-
-struct gliutable {
-	unsigned long desc_name;
-	unsigned short desc_type;
-	unsigned long hi, lo;
-};
-
-struct gliutable gliu0table[] = {
-	{.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = 0x0FFF80},	/*  0-7FFFF to MC */
-	{.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0,.lo = (0x80 << 20) + 0x0FFFE0},	/*  80000-9ffff to Mc */
-	{.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_MC + 0x0,.lo = 0x03},	/*  C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
-	{.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_MC,.lo = 0x0},	/*  Catch and fix dynamicly. */
-	{.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM,.hi = MSR_MC,.lo = 0x0},	/*  Catch and fix dynamicly. */
-	{.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =
-	 GL0_CPU},
-	{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
-};
-
-struct gliutable gliu1table[] = {
-	{.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80},	/*  0-7FFFF to MC */
-	{.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0},	/*  80000-9ffff to Mc */
-	{.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03},	/*  C0000-Fffff split to MC and PCI (sub decode) */
-	{.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0},	/*      Catch and fix dynamicly. */
-	{.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0},	/*      Catch and fix dynamicly. */
-	{.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo =
-	 GL1_GLIU0},
-	{.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0},	/*  FooGlue FPU 0xF0 */
-	{.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0},
-};
-
-struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
-
-struct msrinit {
-	unsigned long msrnum;
-	msr_t msr;
-};
-
-struct msrinit ClockGatingDefault[] = {
-	{GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
-	{MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
-	{VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
-	{GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
-	{DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0555}},
-	{GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
-	{GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0014}},
-	{GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
-	{VIP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
-	{AES_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
-	{CPU_BC_PMODE_MSR, {.hi = 0x00,.lo = 0x70303}},
-	{0xffffffff, {0xffffffff, 0xffffffff}},
-};
-
-/* */
-/*  SET GeodeLink PRIORITY*/
-/* */
-struct msrinit GeodeLinkPriorityTable[] = {
-	{CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}},
-	{DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}},
-	{VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}},
-	{GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}},
-	{GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0017}},
-	{GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}},
-	{VIP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}},
-	{AES_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0013}},
-	{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}},	/*  END */
-};
-
-
-static void writeglmsr(struct gliutable *gl)
-{
-	msr_t msr;
-
-	msr.lo = gl->lo;
-	msr.hi = gl->hi;
-	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
-}
-
-static void ShadowInit(struct gliutable *gl)
-{
-	msr_t msr;
-
-	msr = rdmsr(gl->desc_name);
-
-	if (msr.lo == 0) {
-		writeglmsr(gl);
-	}
-}
-
-static void SysmemInit(struct gliutable *gl)
-{
-	msr_t msr;
-	int sizembytes, sizebytes;
-
-	/*
-	 * Figure out how much RAM is in the machine and allocate all to the
-	 * system. We will adjust for SMM now and Frame Buffer later.
-	 */
-	sizembytes = sizeram();
-	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
-	sizebytes = sizembytes << 20;
-
-	sizebytes -= ((SMM_SIZE * 1024) + 1);
-	printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
-
-	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
-	   The top 8 bits go into 0-7 of msr.hi. */
-	sizebytes--;
-	msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
-	sizebytes <<= 8;	/* move bits 23:12 in bits 31:20. */
-	sizebytes &= 0xfff00000;
-	sizebytes |= 0x100;	/* start at 1MB */
-	msr.lo = sizebytes;
-
-	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
-		     gl->desc_name, msr.hi, msr.lo);
-}
-
-static void SMMGL0Init(struct gliutable *gl)
-{
-	msr_t msr;
-	int sizebytes = sizeram() << 20;
-	long offset;
-
-	sizebytes -= (SMM_SIZE * 1024);
-
-	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
-
-	/* calculate the Two's complement offset */
-	offset = sizebytes - SMM_OFFSET;
-	offset = (offset >> 12) & 0x000fffff;
-	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
-
-	msr.hi = offset << 8 | gl->hi;
-	msr.hi |= SMM_OFFSET >> 24;
-
-	msr.lo = (SMM_OFFSET & 0x00ffffff) << 8;
-	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
-
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
-		     gl->desc_name, msr.hi, msr.lo);
-}
-
-static void SMMGL1Init(struct gliutable *gl)
-{
-	msr_t msr;
-	printk(BIOS_DEBUG, "%s:\n", __func__);
-
-	msr.hi = gl->hi;
-	/* I don't think this is needed */
-	msr.hi &= 0xffffff00;
-	msr.hi |= (SMM_OFFSET >> 24);
-	msr.lo = (SMM_OFFSET & 0x00fff000) << 8;
-	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
-
-	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
-		     gl->desc_name, msr.hi, msr.lo);
-}
-
-static void GLIUInit(struct gliutable *gl)
-{
-
-	while (gl->desc_type != GL_END) {
-		switch (gl->desc_type) {
-		default:
-			/* For Unknown types: Write then read MSR */
-			writeglmsr(gl);
-		case SC_SHADOW:	/*  Check for a Shadow entry */
-			ShadowInit(gl);
-			break;
-
-		case R_SYSMEM:	/*  check for a SYSMEM entry */
-			SysmemInit(gl);
-			break;
-
-		case BMO_SMM:	/*  check for a SMM entry */
-			SMMGL0Init(gl);
-			break;
-
-		case BM_SMM:	/*  check for a SMM entry */
-			SMMGL1Init(gl);
-			break;
-		}
-		gl++;
-	}
-
-}
-
-	/* ************************************************************************** */
-	/* * */
-	/* *    GLPCIInit */
-	/* * */
-	/* *    Set up GLPCI settings for reads/write into memory */
-	/* *    R0:  0-640KB, */
-	/* *    R1:  1MB - Top of System Memory */
-	/* *    R2: SMM Memory */
-	/* *    R3: Framebuffer? - not set up yet */
-	/* *    R4: ?? */
-	/* * */
-	/* *    Entry: */
-	/* *    Exit: */
-	/* *    Modified: */
-	/* * */
-	/* ************************************************************************** */
-static void GLPCIInit(void)
-{
-	struct gliutable *gl = NULL;
-	int i;
-	msr_t msr;
-	int msrnum, enable_preempt, enable_cpu_override;
-	int nic_grants_control, enable_bus_parking;
-
-	/* */
-	/*  R0 - GLPCI settings for Conventional Memory space. */
-	/* */
-	msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;	/* 640 */
-	msr.lo = 0;		/* 0 */
-	msr.lo |=
-	    GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET +
-	    GLPCI_RC_LOWER_WC_SET;
-	msrnum = GLPCI_RC0;
-	wrmsr(msrnum, msr);
-
-	/* */
-	/*  R1 - GLPCI settings for SysMem space. */
-	/* */
-	/*  Get systop from GLIU0 SYSTOP Descriptor */
-	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
-		if (gliu0table[i].desc_type == R_SYSMEM) {
-			gl = &gliu0table[i];
-			break;
-		}
-	}
-	if (gl) {
-		unsigned long pah, pal;
-		msrnum = gl->desc_name;
-		msr = rdmsr(msrnum);
-		/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
-		 * translates to a base of 0x00100000 and top of 0xffbf0000
-		 * base of 1M and top of around 256M
-		 */
-		/* we have to create a page-aligned (4KB page) address for base and top */
-		/* So we need a high page aligned address (pah) and low page aligned address (pal)
-		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
-		 */
-		pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);
-		/* we have the page address. Now make it a page-aligned address */
-		pah <<= 12;
-
-		pal = msr.lo << 12;
-		msr.hi = pah;
-		msr.lo = pal;
-		msr.lo |=
-		    GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
-		    GLPCI_RC_LOWER_WC_SET;
-		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
-			     msr.lo, msr.hi);
-		msrnum = GLPCI_RC1;
-		wrmsr(msrnum, msr);
-	}
-
-	/* */
-	/*      R2 - GLPCI settings for SMM space */
-	/* */
-	msr.hi =
-	    ((SMM_OFFSET +
-	      (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
-	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
-	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
-	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
-		     msr.hi);
-	msrnum = GLPCI_RC2;
-	wrmsr(msrnum, msr);
-
-	/* this is done elsewhere already, but it does no harm to do it more than once */
-	/*  write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
-	msr.lo = 0x021212121;	/* cache disabled and write serialized */
-	msr.hi = 0x021212121;	/* cache disabled and write serialized */
-
-	msrnum = CPU_RCONF_A0_BF;
-	wrmsr(msrnum, msr);
-
-	msrnum = CPU_RCONF_C0_DF;
-	wrmsr(msrnum, msr);
-
-	msrnum = CPU_RCONF_E0_FF;
-	wrmsr(msrnum, msr);
-
-	/*  Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
-	msrnum = GLPCI_A0_BF;
-	msr.hi = 0x35353535;
-	msr.lo = 0x35353535;
-	wrmsr(msrnum, msr);
-
-	msrnum = GLPCI_C0_DF;
-	msr.hi = 0x35353535;
-	msr.lo = 0x35353535;
-	wrmsr(msrnum, msr);
-
-	msrnum = GLPCI_E0_FF;
-	msr.hi = 0x35353535;
-	msr.lo = 0x35353535;
-	wrmsr(msrnum, msr);
-
-	/*  Set WSREQ */
-	msrnum = CPU_DM_CONFIG0;
-	msr = rdmsr(msrnum);
-	msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
-	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT;	/* reduce to 1 for safe mode */
-	wrmsr(msrnum, msr);
-
-	/* we are ignoring the 5530 case for now, and perhaps forever. */
-
-	/* */
-	/* 553x NB Init */
-	/* */
-
-	/* Arbiter setup */
-	enable_preempt =
-	    GLPCI_ARB_LOWER_PRE0_SET | GLPCI_ARB_LOWER_PRE1_SET |
-	    GLPCI_ARB_LOWER_PRE2_SET | GLPCI_ARB_LOWER_CPRE_SET;
-	enable_cpu_override = GLPCI_ARB_LOWER_COV_SET;
-	enable_bus_parking = GLPCI_ARB_LOWER_PARK_SET;
-	nic_grants_control =
-	    (0x4 << GLPCI_ARB_UPPER_R2_SHIFT) | (0x3 <<
-						 GLPCI_ARB_UPPER_H2_SHIFT);
-
-	msrnum = GLPCI_ARB;
-	msr = rdmsr(msrnum);
-
-	msr.hi |= nic_grants_control;
-	msr.lo |= enable_cpu_override | enable_preempt | enable_bus_parking;
-	wrmsr(msrnum, msr);
-
-	msrnum = GLPCI_CTRL;
-	msr = rdmsr(msrnum);
-
-	msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET;	/*   (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
-	msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
-
-	msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
-	msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
-
-	msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
-	msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
-
-	msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
-	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
-
-	msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
-	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
-
-	msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
-	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
-
-	msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
-	msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
-
-	msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
-	msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
-	wrmsr(msrnum, msr);
-
-	/* Set GLPCI Latency Timer */
-	msrnum = GLPCI_CTRL;
-	msr = rdmsr(msrnum);
-	msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT;	/* Change once 1.x is gone */
-	wrmsr(msrnum, msr);
-
-	/*  GLPCI_SPARE */
-	msrnum = GLPCI_SPARE;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~0x7;
-	msr.lo |=
-	    GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET |
-	    GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET |
-	    GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
-	wrmsr(msrnum, msr);
-}
-
-	/* ************************************************************************** */
-	/* * */
-	/* *    ClockGatingInit */
-	/* * */
-	/* *    Enable Clock Gating. */
-	/* * */
-	/* *    Entry: */
-	/* *    Exit: */
-	/* *    Modified: */
-	/* * */
-	/* ************************************************************************** */
-static void ClockGatingInit(void)
-{
-	msr_t msr;
-	struct msrinit *gating = ClockGatingDefault;
-	int i;
-
-	for (i = 0; gating->msrnum != 0xffffffff; i++) {
-		msr = rdmsr(gating->msrnum);
-		msr.hi |= gating->msr.hi;
-		msr.lo |= gating->msr.lo;
-		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
-		   gating->msrnum, msr.hi, msr.lo); */// GX3
-		wrmsr(gating->msrnum, msr);	// MSR - See the table above
-		gating += 1;
-	}
-
-}
-
-static void GeodeLinkPriority(void)
-{
-	msr_t msr;
-	struct msrinit *prio = GeodeLinkPriorityTable;
-	int i;
-
-	for (i = 0; prio->msrnum != 0xffffffff; i++) {
-		msr = rdmsr(prio->msrnum);
-		msr.hi |= prio->msr.hi;
-		msr.lo &= ~0xfff;
-		msr.lo |= prio->msr.lo;
-		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
-		   prio->msrnum, msr.hi, msr.lo);  */// GX3
-		wrmsr(prio->msrnum, msr);	// MSR - See the table above
-		prio += 1;
-	}
-}
-
-/*
- *	Get the GLIU0 shadow register settings
- *	If the setShadow function is used then all shadow descriptors
- *	  will stay sync'ed.
- */
-static uint64_t getShadow(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(MSR_GLIU0_SHADOW);
-	return (((uint64_t) msr.hi) << 32) | msr.lo;
-}
-
-/*
- *	Set the cache RConf registers for the memory hole.
- *	Keeps all cache shadow descriptors sync'ed.
- *	This is part of the PCI lockup solution
- *	Entry: EDX:EAX is the shadow settings
- */
-static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
-{
-
-	// ok this is whacky bit translation time.
-	int bit;
-	uint8_t shadowByte;
-	msr_t msr = { 0, 0 };
-	shadowByte = (uint8_t) (shadowLo >> 16);
-
-	// load up D000 settings in edx.
-	for (bit = 7; bit >= 4; bit--) {
-		msr.hi <<= 8;
-		msr.hi |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte & (1 << bit))
-			msr.hi |= 0x20;	// write serialize PCI memory
-	}
-
-	// load up C000 settings in eax.
-	for (; bit >= 0; bit--) {
-		msr.lo <<= 8;
-		msr.lo |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte & (1 << bit))
-			msr.lo |= 0x20;	// write serialize PCI memory
-	}
-
-	wrmsr(CPU_RCONF_C0_DF, msr);
-
-	shadowByte = (uint8_t) (shadowLo >> 24);
-
-	// load up F000 settings in edx.
-	for (bit = 7; bit >= 4; bit--) {
-		msr.hi <<= 8;
-		msr.hi |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte & (1 << bit))
-			msr.hi |= 0x20;	// write serialize PCI memory
-	}
-
-	// load up E000 settings in eax.
-	for (; bit >= 0; bit--) {
-		msr.lo <<= 8;
-		msr.lo |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte & (1 << bit))
-			msr.lo |= 0x20;	// write serialize PCI memory
-	}
-
-	wrmsr(CPU_RCONF_E0_FF, msr);
-}
-
-/*
- *	Set the GLPCI registers for the memory hole.
- *	Keeps all cache shadow descriptors sync'ed.
- *	Entry: EDX:EAX is the shadow settings
- */
-static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
-{
-	msr_t msr;
-
-// Set the Enable Register.
-	msr = rdmsr(GLPCI_REN);
-	msr.lo &= 0xFFFF00FF;
-	msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);
-	wrmsr(GLPCI_REN, msr);
-}
-
-/*
- *	Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
- *	Keeps all shadow descriptors sync'ed.
- *	Entry: EDX:EAX is the shadow settings
- */
-static void setShadow(uint64_t shadowSettings)
-{
-	int i;
-	msr_t msr;
-	struct gliutable *pTable;
-	uint32_t shadowLo, shadowHi;
-
-	shadowLo = (uint32_t) shadowSettings;
-	shadowHi = (uint32_t) (shadowSettings >> 32);
-
-	setShadowRCONF(shadowHi, shadowLo);
-	setShadowGLPCI(shadowHi, shadowLo);
-
-	for (i = 0; gliutables[i]; i++) {
-		for (pTable = gliutables[i]; pTable->desc_type != GL_END;
-		     pTable++) {
-			if (pTable->desc_type == SC_SHADOW) {
-
-				msr = rdmsr(pTable->desc_name);
-				msr.lo = (uint32_t) shadowSettings;
-				msr.hi &= 0xFFFF0000;	// maintain PDID in upper EDX
-				msr.hi |=
-				    ((uint32_t) (shadowSettings >> 32)) &
-				    0x0000FFFF;
-				wrmsr(pTable->desc_name, msr);	// MSR - See the table above
-			}
-		}
-	}
-}
-
-static void rom_shadow_settings(void)
-{
-
-	uint64_t shadowSettings = getShadow();
-	shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL;	// Disable read & writes
-	shadowSettings |= (uint64_t) 0x00000000F0000000ULL;	// Enable reads for F0000-FFFFF
-	shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL;	// Enable rw for C0000-CFFFF
-	setShadow(shadowSettings);
-}
-
-/***************************************************************************
- *
- * L1Init
- *	  Set up RCONF_DEFAULT and any other RCONF registers needed
- *
- *  DEVRC_RCONF_DEFAULT:
- *  ROMRC(63:56) = 04h	 ; write protect ROMBASE
- *  ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
- *  DEVRC(35:28) =  39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
- *  SYSTOP(27:8) = top of system memory
- *  SYSRC(7:0) = 00h	 ; writeback, can set to 08h to make writethrough
- *
- ***************************************************************************/
-#define SYSMEM_RCONF_WRITETHROUGH 8
-#define DEVRC_RCONF_DEFAULT 0x21ul
-#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
-#define ROMRC_RCONF_DEFAULT 0x25
-
-static void enable_L1_cache(void)
-{
-	struct gliutable *gl = NULL;
-	int i;
-	msr_t msr;
-	uint8_t SysMemCacheProp;
-
-	/* Locate SYSMEM entry in GLIU0table */
-	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
-		if (gliu0table[i].desc_type == R_SYSMEM) {
-			gl = &gliu0table[i];
-			break;
-		}
-	}
-	if (gl == 0) {
-		post_code(0xCE);	/* POST_RCONFInitError */
-		while (1) ;
-	}
-// sysdescfound:
-	msr = rdmsr(gl->desc_name);
-
-	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the
-	 * top 8 bits go into 0-7 of edx.
-	 */
-	msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
-	msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
-	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	// 8
-
-	// Set Default SYSMEM region properties
-	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	// NOT writethrough == writeback 8 (or ~8)
-
-	// Set PCI space cache properties
-	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	// setting is split betwwen hi and lo...
-	msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
-
-	// Set the ROMBASE. This is usually FFFC0000h
-	msr.hi |=
-	    (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
-
-	// Set ROMBASE cache properties.
-	msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
-
-	// now program RCONF_DEFAULT
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
-		     msr.lo);
-
-	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
-	// Set to match system memory cache properties.
-	msr = rdmsr(CPU_RCONF_DEFAULT);
-	SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
-	msr = rdmsr(CPU_RCONF_BYPASS);
-	msr.lo =
-	    (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
-	wrmsr(CPU_RCONF_BYPASS, msr);
-
-	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
-		     msr.lo);
-}
-
-static void enable_L2_cache(void)
-{
-	msr_t msr;
-
-	/* Instruction Memory Configuration register
-	 * set EBE bit, required when L2 cache is enabled
-	 */
-	msr = rdmsr(CPU_IM_CONFIG);
-	msr.lo |= 0x400;
-	wrmsr(CPU_IM_CONFIG, msr);
-
-	/* Data Memory Subsystem Configuration register
-	 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
-	 */
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= 0x4000;
-	wrmsr(CPU_DM_CONFIG0, msr);
-
-	/* invalidate L2 cache */
-	msr.hi = 0x00;
-	msr.lo = 0x10;
-	wrmsr(CPU_BC_L2_CONF, msr);
-
-	/* Enable L2 cache */
-	msr.hi = 0x00;
-	msr.lo = 0x0f;
-	wrmsr(CPU_BC_L2_CONF, msr);
-
-	printk(BIOS_DEBUG, "L2 cache enabled\n");
-}
-
-static void setup_lx_cache(void)
-{
-	msr_t msr;
-
-	enable_L1_cache();
-	enable_L2_cache();
-
-	// Make sure all INVD instructions are treated as WBINVD.  We do this
-	// because we've found some programs which require this behavior.
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
-	wrmsr(CPU_DM_CONFIG0, msr);
-
-	x86_enable_cache();
-	wbinvd();
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	uint32_t systop;
-	msr_t msr;
-
-	msr = rdmsr(MSR_GLIU0_SYSMEM);
-	systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
-	systop += 0x1000;	/* 4K */
-
-	return systop;
-}
-
-/****************************************************************************/
-/* *	northbridge_init_early */
-/* **/
-/* *	Core Logic initialization:  Host bridge*/
-/* **/
-/* ***************************************************************************/
-void northbridge_init_early(void)
-{
-	int i;
-	printk(BIOS_DEBUG, "Enter %s\n", __func__);
-
-	for (i = 0; gliutables[i]; i++)
-		GLIUInit(gliutables[i]);
-
-	/*  Now that the descriptor to memory is set up. */
-	/*  The memory controller needs one read to synch its lines before it can be used. */
-	read32(zeroptr);
-
-	GeodeLinkPriority();
-
-	setup_lx_cache();
-
-	rom_shadow_settings();
-
-	GLPCIInit();
-
-	ClockGatingInit();
-
-	__asm__ __volatile__("FINIT\n");
-	printk(BIOS_DEBUG, "Exit %s\n", __func__);
-}
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
deleted file mode 100644
index cb332ead12..0000000000
--- a/src/northbridge/amd/lx/pll_reset.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include "northbridge.h"
-
-void lx_pll_reset(void)
-{
-	msr_t msrGlcpSysRstpll;
-
-	msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
-
-	printk(BIOS_DEBUG, "MSR GLCP_SYS_RSTPLL (%08x) value is %08x:%08x\n",
-		GLCP_SYS_RSTPLL, msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo);
-
-	post_code(POST_PLL_INIT);
-
-	if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
-		printk(BIOS_DEBUG, "Configuring PLL.\n");
-		if (CONFIG_PLL_MANUAL_CONFIG) {
-			post_code(POST_PLL_MANUAL);
-			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
-			msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi;
-
-			/* Hold Count - how long we will sit in reset */
-			msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo;
-		} else {
-			/*automatic configuration (straps) */
-			post_code(POST_PLL_STRAP);
-			msrGlcpSysRstpll.lo &=
-			    ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
-			msrGlcpSysRstpll.lo |=
-			    (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
-			msrGlcpSysRstpll.lo &=
-			    ~(RSTPPL_LOWER_COREBYPASS_SET |
-			      RSTPPL_LOWER_MBBYPASS_SET);
-			msrGlcpSysRstpll.lo |=
-			    RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET;
-		}
-		/* Use SWFLAGS to remember: "we've already been here"  */
-		msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
-
-		/* "reset the chip" value */
-		msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
-		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
-
-		/* You should never get here..... The chip has reset. */
-		post_code(POST_PLL_RESET_FAIL);
-		die("CONFIGURING PLL FAILURE\n");
-
-	}
-	printk(BIOS_DEBUG, "PLL configured.\n");
-	return;
-}
-
-unsigned int GeodeLinkSpeed(void)
-{
-	unsigned int speed;
-	msr_t msr;
-
-	msr = rdmsr(GLCP_SYS_RSTPLL);
-	speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
-	if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
-		++speed;
-	}
-	return (speed);
-}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
deleted file mode 100644
index 8de85a346e..0000000000
--- a/src/northbridge/amd/lx/raminit.c
+++ /dev/null
@@ -1,775 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <arch/io.h>
-#include <spd.h>
-#include <stddef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include "raminit.h"
-#include "northbridge.h"
-
-static const unsigned char NumColAddr[] = {
-	0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
-	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
-};
-
-static void banner(const char *s)
-{
-	printk(BIOS_DEBUG, " * %s\n", s);
-}
-
-static void __noreturn hcf(void)
-{
-	printk(BIOS_EMERG, "DIE\n");
-	/* this guarantees we flush the UART fifos (if any) and also
-	 * ensures that things, in general, keep going so no debug output
-	 * is lost
-	 */
-	while (1)
-		printk(BIOS_EMERG, "%c", 0);
-}
-
-static void auto_size_dimm(unsigned int dimm)
-{
-	uint32_t dimm_setting;
-	uint16_t dimm_size;
-	uint8_t spd_byte;
-	msr_t msr;
-
-	dimm_setting = 0;
-
-	banner("Check present");
-	/* Check that we have a dimm */
-	if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
-		return;
-	}
-
-	banner("MODBANKS");
-	/* Field: Module Banks per DIMM */
-	/* EEPROM byte usage: (5) Number of DIMM Banks */
-	spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
-	if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
-		printk(BIOS_EMERG, "Number of module banks not compatible\n");
-		post_code(ERROR_BANK_SET);
-		hcf();
-	}
-	dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
-	banner("FIELDBANKS");
-
-	/* Field: Banks per SDRAM device */
-	/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
-	spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
-	if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
-		printk(BIOS_EMERG, "Number of device banks not compatible\n");
-		post_code(ERROR_BANK_SET);
-		hcf();
-	}
-	dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
-	banner("SPDNUMROWS");
-
-	/*; Field: DIMM size
-	 *; EEPROM byte usage: (3)  Number of Row Addresses
-	 *;                                       (4)  Number of Column Addresses
-	 *;                                       (5)  Number of DIMM Banks
-	 *;                                       (31) Module Bank Density
-	 *; Size = Module Density * Module Banks
-	 */
-	if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
-	    || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
-		printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
-		post_code(ERROR_UNSUPPORTED_DIMM);
-		hcf();
-	}
-	banner("SPDBANKDENSITY");
-
-	dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
-	banner("DIMMSIZE");
-	dimm_size |= (dimm_size << 8);	/* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
-	dimm_size &= 0x01FC;	/* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
-
-	/*       Module Density * Module Banks */
-	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;	/* shift to multiply by # DIMM banks */
-	banner("BEFORT CTZ");
-	dimm_size = __builtin_ctz(dimm_size);
-	banner("TEST DIMM SIZE > 8");
-	if (dimm_size > 8) {	/* 8 is 1GB only support 1GB per DIMM */
-		printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
-		post_code(ERROR_DENSITY_DIMM);
-		hcf();
-	}
-	dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
-	banner("PAGESIZE");
-
-/*; Field: PAGE size
-*; EEPROM byte usage: (4)  Number of Column Addresses
-*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
-*
-*; But this really works by magic.
-*;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
-*;that MC generates, here is how the MC assigns the pa onto the ma pins:
-*
-*;ma  12 11 10 09 08 07 06 05 04 03 02 01 00
-*;-------------------------------------------
-*;pa					09 08 07 06 05 04 03	(7 col addr bits = 1K page size)
-*;pa				 10 09 08 07 06 05 04 03	(8 col addr bits = 2K page size)
-*;pa			  11 10 09 08 07 06 05 04 03	(9 col addr bits = 4K page size)
-*;pa		   12 11 10 09 08 07 06 05 04 03	(10 col addr bits = 8K page size)
-*;pa	 13 AP 12 11 10 09 08 07 06 05 04 03	(11 col addr bits = 16K page size)
-*;pa  14 13 AP 12 11 10 09 08 07 06 05 04 03	(12 col addr bits = 32K page size)
-*; *AP = autoprecharge bit
-*
-*;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
-*;so lower 3 address bits are dont_cares.So from the table above,
-*;it's easier to see what the old code is doing: if for example,#col_addr_bits = 7(06h),
-*;it adds 3 to get 10, then does 2^10 = 1K.  Get it?*/
-
-	spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
-	banner("MAXCOLADDR");
-	if (spd_byte > MAX_COL_ADDR) {
-		printk(BIOS_EMERG, "DIMM page size not compatible\n");
-		post_code(ERROR_SET_PAGE);
-		hcf();
-	}
-	banner(">12address test");
-	spd_byte -= 7;
-	if (spd_byte > 5) {	/* if the value is above 6 it means > 12 address lines */
-		spd_byte = 7;	/* which means > 32k so set to disabled */
-	}
-	dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT;	/* 0 = 1k, 1 = 2k, 2 = 4k, etc */
-
-	banner("RDMSR CF07");
-	msr = rdmsr(MC_CF07_DATA);
-	banner("WRMSR CF07");
-	if (dimm == DIMM0) {
-		msr.hi &= 0xFFFF0000;
-		msr.hi |= dimm_setting;
-	} else {
-		msr.hi &= 0x0000FFFF;
-		msr.hi |= dimm_setting << 16;
-	}
-	wrmsr(MC_CF07_DATA, msr);
-	banner("ALL DONE");
-}
-
-static void checkDDRMax(void)
-{
-	uint8_t spd_byte0, spd_byte1;
-	uint16_t speed;
-
-	/* PC133 identifier */
-	spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-
-	/* I don't think you need this check.
-	   if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0) {
-	   printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
-	   post_code(POST_PLL_MEM_FAIL);
-	   hcf();
-	   } */
-
-	/* Use the slowest DIMM */
-	if (spd_byte0 < spd_byte1) {
-		spd_byte0 = spd_byte1;
-	}
-
-	/* Turn SPD ns time into MHz. Check what the asm does to this math. */
-	speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
-
-	/* current speed > max speed? */
-	if (GeodeLinkSpeed() > speed) {
-		printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
-		post_code(POST_PLL_MEM_FAIL);
-		hcf();
-	}
-}
-
-const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 };	/* ns */
-
-static void set_refresh_rate(void)
-{
-	uint8_t spd_byte0, spd_byte1;
-	uint16_t rate0, rate1;
-	msr_t msr;
-
-	spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
-	spd_byte0 &= 0xF;
-	if (spd_byte0 > 5) {
-		spd_byte0 = 5;
-	}
-	rate0 = REF_RATE[spd_byte0];
-
-	spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
-	spd_byte1 &= 0xF;
-	if (spd_byte1 > 5) {
-		spd_byte1 = 5;
-	}
-	rate1 = REF_RATE[spd_byte1];
-
-	/* Use the faster rate (lowest number) */
-	if (rate0 > rate1) {
-		rate0 = rate1;
-	}
-
-	msr = rdmsr(MC_CF07_DATA);
-	msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
-			<< CF07_LOWER_REF_INT_SHIFT;
-	wrmsr(MC_CF07_DATA, msr);
-}
-
-const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 };	/* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
-
-static u8 getcasmap(u32 dimm, u16 glspeed)
-{
-	u16 dimm_speed;
-	u8 spd_byte, casmap, casmap_shift = 0;
-
-	/**************************	 DIMM0	**********************************/
-	casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
-	if (casmap != 0xFF) {
-		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
-		spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
-		if (spd_byte != 0) {
-			/* Turn SPD ns time into MHz. Check what the asm does to this math. */
-			dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
-			if (dimm_speed >= glspeed) {
-				casmap_shift = 1; /* -.5 is a shift of 1 */
-				/* IF -1 timing is supported, check -1 timing > GeodeLink */
-				spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
-				if (spd_byte != 0) {
-					/* Turn SPD ns time into MHz. Check what the asm does to this math. */
-					dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
-					if (dimm_speed >= glspeed) {
-						casmap_shift = 2; /* -1 is a shift of 2 */
-					}
-				}	/* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
-			} else {
-				casmap_shift = 0;
-			}
-		}	/* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
-		/* set the casmap based on the shift to limit possible CAS settings */
-		spd_byte = 31 - __builtin_clz((uint32_t) casmap);
-		/* just want bits in the lower byte since we have to cast to a 32 */
-		casmap &= 0xFF << (spd_byte - casmap_shift);
-	} else {		/* No DIMM */
-		casmap = 0;
-	}
-	return casmap;
-}
-
-static void setCAS(void)
-{
-/*;*****************************************************************************
-;*
-;*	setCAS
-;*	EEPROM byte usage: (18) SDRAM device attributes - CAS latency
-;*	EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
-;*	EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
-;*
-;*	The CAS setting is based on the information provided in each DIMMs SPD.
-;*	 The speed at which a DIMM can run is described relative to the slowest
-;*	 CAS the DIMM supports. Each speed for the relative CAS settings is
-;*	 checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
-;*	 speed, the CAS setting	 is removed from the list of good settings for
-;*	 the DIMM. This is done for both DIMMs and the lists are compared to
-;*	 find the lowest common CAS latency setting. If there are no CAS settings
-;*	 in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
-;*
-;*	Entry:
-;*	Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
-;*	Destroys: We really use everything !
-;*****************************************************************************/
-	uint16_t glspeed;
-	uint8_t spd_byte, casmap0, casmap1;
-	msr_t msr;
-
-	glspeed = GeodeLinkSpeed();
-
-	casmap0 = getcasmap(DIMM0, glspeed);
-	casmap1 = getcasmap(DIMM1, glspeed);
-
-	/*********************	CAS_LAT MAP COMPARE	***************************/
-	if (casmap0 == 0) {
-		spd_byte = CASDDR[__builtin_ctz(casmap1)];
-	} else if (casmap1 == 0) {
-		spd_byte = CASDDR[__builtin_ctz(casmap0)];
-	} else if ((casmap0 &= casmap1)) {
-		spd_byte = CASDDR[__builtin_ctz(casmap0)];
-	} else {
-		printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
-		post_code(ERROR_DIFF_DIMMS);
-		hcf();
-	}
-
-	msr = rdmsr(MC_CF8F_DATA);
-	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
-	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
-	wrmsr(MC_CF8F_DATA, msr);
-}
-
-static void set_latencies(void)
-{
-	uint32_t memspeed, dimm_setting;
-	uint8_t spd_byte0, spd_byte1;
-	msr_t msr;
-
-	memspeed = GeodeLinkSpeed() / 2;
-	dimm_setting = 0;
-
-	/* MC_CF8F setup */
-	/* tRAS */
-	spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
-		spd_byte0 = spd_byte1;
-	}
-
-	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = (spd_byte0 * memspeed) / 1000;
-	if (((spd_byte0 * memspeed) % 1000)) {
-		++spd_byte1;
-	}
-	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
-
-	/* tRP */
-	spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
-		spd_byte0 = spd_byte1;
-	}
-
-	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
-	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
-		++spd_byte1;
-	}
-	dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
-
-	/* tRCD */
-	spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
-		spd_byte0 = spd_byte1;
-	}
-
-	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
-	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
-		++spd_byte1;
-	}
-	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
-
-	/* tRRD */
-	spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
-		spd_byte0 = spd_byte1;
-	}
-
-	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
-	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
-	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
-		++spd_byte1;
-	}
-	dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
-
-	/* tRC = tRP + tRAS */
-	dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
-			 ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
-			<< CF8F_LOWER_ACT2ACTREF_SHIFT;
-
-	msr = rdmsr(MC_CF8F_DATA);
-	msr.lo &= 0xF00000FF;
-	msr.lo |= dimm_setting;
-	msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
-	wrmsr(MC_CF8F_DATA, msr);
-
-	/* MC_CF1017 setup */
-	/* tRFC */
-	spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-	if (spd_byte0 < spd_byte1) {
-		spd_byte0 = spd_byte1;
-	}
-
-	if (spd_byte0) {
-		/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
-		spd_byte1 = (spd_byte0 * memspeed) / 1000;
-		if (((spd_byte0 * memspeed) % 1000)) {
-			++spd_byte1;
-		}
-	} else {		/* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
-		spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
-	}
-	dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT;	/* note this clears the cf8f dimm setting */
-	msr = rdmsr(MC_CF1017_DATA);
-	msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
-	msr.lo |= dimm_setting;
-	wrmsr(MC_CF1017_DATA, msr);
-
-	/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200MHz mem) other wise it stay default(1) */
-	if (memspeed > 198) {
-		msr = rdmsr(MC_CF1017_DATA);
-		msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
-		msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
-		wrmsr(MC_CF1017_DATA, msr);
-	}
-}
-
-static void set_extended_mode_registers(void)
-{
-	uint8_t spd_byte0, spd_byte1;
-	msr_t msr;
-	spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
-	if (spd_byte0 == 0xFF) {
-		spd_byte0 = 0;
-	}
-	spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
-	if (spd_byte1 == 0xFF) {
-		spd_byte1 = 0;
-	}
-	spd_byte1 &= spd_byte0;
-
-	msr = rdmsr(MC_CF07_DATA);
-	if (spd_byte1 & 1) {	/* Drive Strength Control */
-		msr.lo |= CF07_LOWER_EMR_DRV_SET;
-	}
-	if (spd_byte1 & 2) {	/* FET Control */
-		msr.lo |= CF07_LOWER_EMR_QFC_SET;
-	}
-	wrmsr(MC_CF07_DATA, msr);
-}
-
-#undef TLA_MEMORY_DEBUG
-#ifdef TLA_MEMORY_DEBUG
-static void EnableMTest(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(GLCP_DELAY_CONTROLS);
-	msr.hi &= ~(7 << 20);	/* clear bits 54:52 */
-	if (GeodeLinkSpeed() < 200) {
-		msr.hi |= 2 << 20;
-	}
-	wrmsr(GLCP_DELAY_CONTROLS, msr);
-
-	msr = rdmsr(MC_CFCLK_DBUG);
-	msr.hi |=
-	    CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
-	    CFCLK_UPPER_MTST_RBEX_EN_SET;
-	msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
-	wrmsr(MC_CFCLK_DBUG, msr);
-
-	printk(BIOS_INFO, "Enabled MTest for TLA debug\n");
-}
-#endif
-
-void sdram_set_registers(const struct mem_controller *ctrl)
-{
-	msr_t msr;
-	uint32_t msrnum;
-
-	/* Set Timing Control */
-	msrnum = MC_CF1017_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
-	if (GeodeLinkSpeed() < 334) {
-		msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
-	} else {
-		msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
-	}
-	wrmsr(msrnum, msr);
-
-	/* Set Refresh Staggering */
-	msrnum = MC_CF07_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~0xF0;
-	msr.lo |= 0x40;		/* set refresh to 4SDRAM clocks */
-	wrmsr(msrnum, msr);
-
-	/* Memory Interleave: Set HOI here otherwise default is LOI */
-	/* msrnum = MC_CF8F_DATA;
-	   msr = rdmsr(msrnum);
-	   msr.hi |= CF8F_UPPER_HOI_LOI_SET;
-	   wrmsr(msrnum, msr); */
-}
-
-void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
-	uint8_t spd_byte;
-
-	banner("sdram_set_spd_register");
-	post_code(POST_MEM_SETUP);	// post_70h
-
-	spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
-	banner("Check DIMM 0");
-	/* Check DIMM is not Register and not Buffered DIMMs. */
-	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
-		post_code(ERROR_UNSUPPORTED_DIMM);
-		hcf();
-	}
-	banner("Check DIMM 1");
-	spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
-	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
-		post_code(ERROR_UNSUPPORTED_DIMM);
-		hcf();
-	}
-
-	post_code(POST_MEM_SETUP2);	// post_72h
-	banner("Check DDR MAX");
-
-	/* Check that the memory is not overclocked. */
-	checkDDRMax();
-
-	/* Size the DIMMS */
-	post_code(POST_MEM_SETUP3);	// post_73h
-	banner("AUTOSIZE DIMM 0");
-	auto_size_dimm(DIMM0);
-	post_code(POST_MEM_SETUP4);	// post_74h
-	banner("AUTOSIZE DIMM 1");
-	auto_size_dimm(DIMM1);
-
-	/* Set CAS latency */
-	banner("set cas latency");
-	post_code(POST_MEM_SETUP5);	// post_75h
-	setCAS();
-
-	/* Set all the other latencies here (tRAS, tRP....) */
-	banner("set all latency");
-	set_latencies();
-
-	/* Set Extended Mode Registers */
-	banner("set emrs");
-	set_extended_mode_registers();
-
-	banner("set ref rate");
-	/* Set Memory Refresh Rate */
-	set_refresh_rate();
-
-}
-
-/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
- * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
-void sdram_enable(int controllers, const struct mem_controller *ctrl)
-{
-	uint32_t i, msrnum;
-	msr_t msr;
-
-/*********************************************************************
-;* Turn on MC/DIMM interface per JEDEC
-;* 1) Clock stabilizes > 200us
-;* 2) Assert CKE
-;* 3) Precharge All to put all banks into an idles state
-;* 4) EMRS to enable DLL
-;* 6) MRS w/ memory config & reset DLL set
-;* 7) Wait 200 clocks (2us)
-;* 8) Precharge All and 2 Auto refresh
-;* 9) MRS w/ memory config & reset DLL clear
-;* 8) DDR SDRAM ready for normal operation
-;********************************************************************/
-	post_code(POST_MEM_ENABLE);	// post_76h
-
-#ifdef TLA_MEMORY_DEBUG
-	/* Only enable MTest for TLA memory debug */
-	EnableMTest();
-#endif
-
-	/* If both Page Size = "Not Installed" we have a problems and should halt. */
-	msr = rdmsr(MC_CF07_DATA);
-	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
-			((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
-		printk(BIOS_EMERG, "No memory in the system\n");
-		post_code(ERROR_NO_DIMMS);
-		hcf();
-	}
-
-	/*      Set CKEs */
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
-	wrmsr(msrnum, msr);
-
-	/* Force Precharge All on next command, EMRS */
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
-	wrmsr(msrnum, msr);
-
-	/* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
-	msrnum = MC_CF07_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
-	wrmsr(msrnum, msr);
-	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
-	wrmsr(msrnum, msr);
-
-	/* Clear Force Precharge All */
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
-	wrmsr(msrnum, msr);
-
-	/* MRS Reset DLL - set */
-	msrnum = MC_CF07_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
-	wrmsr(msrnum, msr);
-	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
-	wrmsr(msrnum, msr);
-
-	/* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */
-	/* Wait 2 PORT61 ticks. between 15us and 30us */
-	/* This would be endless if the timer is stuck. */
-	while ((inb(0x61)));	/* find the first edge */
-	while (!(~inb(0x61)));
-
-	/* Force Precharge All on the next command, auto-refresh */
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
-	wrmsr(msrnum, msr);
-
-	/* Manually AUTO refresh #1 */
-	/* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
-	msrnum = MC_CF07_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo |= CF07_LOWER_REF_TEST_SET;
-	wrmsr(msrnum, msr);
-	msr.lo &= ~CF07_LOWER_REF_TEST_SET;
-	wrmsr(msrnum, msr);
-
-	/* Clear Force Precharge All */
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
-	wrmsr(msrnum, msr);
-
-	/* Manually AUTO refresh */
-	/* The MC should insert the right delay between the refreshes */
-	msrnum = MC_CF07_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo |= CF07_LOWER_REF_TEST_SET;
-	wrmsr(msrnum, msr);
-	msr.lo &= ~CF07_LOWER_REF_TEST_SET;
-	wrmsr(msrnum, msr);
-
-	/* MRS Reset DLL - clear */
-	msrnum = MC_CF07_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo |= CF07_LOWER_PROG_DRAM_SET;
-	wrmsr(msrnum, msr);
-	msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
-	wrmsr(msrnum, msr);
-
-	/* Allow MC to tristate during idle cycles with MTEST OFF */
-	msrnum = MC_CFCLK_DBUG;
-	msr = rdmsr(msrnum);
-	msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
-	wrmsr(msrnum, msr);
-
-	/* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
-	msr = rdmsr(MC_CF07_DATA);
-	if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
-	    (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
-		msrnum = GLCP_DELAY_CONTROLS;
-		msr = rdmsr(msrnum);
-		msr.hi |= (1 << 23);	/* SDCLK bit for 2.0 */
-		wrmsr(msrnum, msr);
-	}
-
-	/* Set PMode0 Sensitivity Counter */
-	msr.lo = 0;		/* pmode 0 = 0 most aggressive */
-	msr.hi = 0x200;		/* pmode 1 = 200h */
-	wrmsr(MC_CF_PMCTR, msr);
-
-	/* Set PMode1 Up delay enable */
-	msrnum = MC_CF1017_DATA;
-	msr = rdmsr(msrnum);
-	msr.lo |= (209 << 8);	/* bits[15:8] = 209 */
-	wrmsr(msrnum, msr);
-
-	banner("DRAM controller init done.\n");
-	post_code(POST_MEM_SETUP_GOOD);	//0x7E
-
-	/* make sure there is nothing stale in the cache */
-	/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
-
-	/* The RAM dll needs a write to lock on so generate a few dummy writes */
-	/* Note: The descriptor needs to be enabled to point at memory */
-	for (i = 0; i < 5; i++) {
-		write32(zeroptr + i, i);
-	}
-	/* SWAPSiF for PBZ 4112 (Errata 34) */
-	/* check for failed DLL settings now that we have done a memory write. */
-	msrnum = GLCP_DELAY_CONTROLS;
-	msr = rdmsr(msrnum);
-	if ((msr.lo & 0x7FF) == 0x104) {
-
-		/* If you had it you would need to clear out the fail boot count flag */
-		/*       (depending on where it counts from etc). */
-
-		/* The reset we are about to perform clears the PM_SSC register in the */
-		/*       5536 so will need to store the S3 resume flag in NVRAM otherwise */
-		/*       it would do a normal boot */
-
-		/* Reset the system */
-		msrnum = MDD_SOFT_RESET;
-		msr = rdmsr(msrnum);
-		msr.lo |= 1;
-		wrmsr(msrnum, msr);
-	}
-	printk(BIOS_INFO, "RAM DLL lock\n");
-
-}
diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h
deleted file mode 100644
index a1c0fcde20..0000000000
--- a/src/northbridge/amd/lx/raminit.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-#include <stdint.h>
-
-#define DIMM_SOCKETS 2
-
-struct mem_controller {
-	uint16_t channel0[DIMM_SOCKETS];
-};
-
-void sdram_set_registers(const struct mem_controller *ctrl);
-void sdram_set_spd_registers(const struct mem_controller *ctrl);
-void sdram_enable(int controllers, const struct mem_controller *ctrl);
-
-void sdram_initialize(int controllers, const struct mem_controller *ctrl);
-
-/* mainboard specific */
-int spd_read_byte(unsigned int device, unsigned int address);
-
-#endif