This patch adds support for the AMD LX cpu.

There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok.  Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.


Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 1971 insertions, 0 deletions

diff --git a/src/northbridge/amd/lx/Config.lb b/src/northbridge/amd/lx/Config.lb
new file mode 100644
index 0000000000..ee8cd206f9
--- /dev/null
+++ b/src/northbridge/amd/lx/Config.lb
@@ -0,0 +1,5 @@
+config chip.h
+object northbridge.o
+object northbridgeinit.o
+object chipsetinit.o
+object grphinit.o
diff --git a/src/northbridge/amd/lx/chip.h b/src/northbridge/amd/lx/chip.h
new file mode 100644
index 0000000000..1a237d7276
--- /dev/null
+++ b/src/northbridge/amd/lx/chip.h
@@ -0,0 +1,7 @@
+struct northbridge_amd_lx_config
+{
+ 	uint16_t irqmap;
+	int setupflash;
+};
+
+extern struct chip_operations northbridge_amd_lx_ops;
diff --git a/src/northbridge/amd/lx/chipsetinit.c b/src/northbridge/amd/lx/chipsetinit.c
new file mode 100644
index 0000000000..0178079795
--- /dev/null
+++ b/src/northbridge/amd/lx/chipsetinit.c
@@ -0,0 +1,384 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "northbridge.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/cache.h>
+
+
+/* the structs in this file only set msr.lo. But ... that may not always be true */
+
+struct msrinit {
+	unsigned long msrnum;
+	msr_t msr;
+};
+
+/*  Master Configuration Register for Bus Masters.*/
+struct msrinit SB_MASTER_CONF_TABLE[] = {
+	{USB1_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},	/*  NOTE: Must be 1st entry in table*/
+	{USB2_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},
+	{ATA_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00048f000}},
+	{AC97_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00008f000}},
+	{MDD_SB_GLD_MSR_CONF,	{.hi=0,.lo=0x00000f000}},
+/* GLPCI_SB_GLD_MSR_CONF,	0x0FFFFFFFF*/
+/* GLCP_SB_GLD_MSR_CONF,	0x0FFFFFFFF*/
+/* GLIU_SB_GLD_MSR_CONF,	0x0*/
+	{0,{0,0}}
+};
+
+/*  5535_A3 Clock Gating*/
+struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
+	{      USB1_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{      USB2_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{      GLIU_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
+	{      GLPCI_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{      GLCP_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
+	{      MDD_SB_GLD_MSR_PM,	{.hi=0,.lo=0x050554111}},
+	{      ATA_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{	AC97_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{0,{0,0}}
+};
+
+/*  5536 Clock Gating*/
+struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
+/* MSR		  Setting*/
+	{      GLIU_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
+	{      GLPCI_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{      GLCP_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000004}},
+	{      MDD_SB_GLD_MSR_PM,	{.hi=0,.lo=0x050554111}}, /*  SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/
+	{      ATA_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{      AC97_SB_GLD_MSR_PM,	{.hi=0,.lo=0x000000005}},
+	{0,{0,0}}
+};
+
+struct acpiinit {
+	unsigned short ioreg; 
+	unsigned long regdata;
+	unsigned short iolen;
+};
+
+struct acpiinit acpi_init_table[] = {
+	{ACPI_BASE+0x00, 0x01000000, 4},
+	{ACPI_BASE+0x08, 0, 4},
+	{ACPI_BASE+0x0C, 0, 4},
+	{ACPI_BASE+0x1C, 0, 4},
+	{ACPI_BASE+0x18, 0x0FFFFFFFF, 4},
+	{ACPI_BASE+0x00, 0x0000FFFF, 4},
+
+	{PM_SCLK, 0x000000E00, 4},
+	{PM_SED,  0x000004601, 4},
+	{PM_SIDD, 0x000008C02, 4},
+	{PM_WKD,  0x0000000A0, 4},
+	{PM_WKXD, 0x0000000A0, 4},
+	{0,0,0}
+};
+
+/* return 1 if we are a 5536-based system */
+static int is_5536(void){
+	msr_t msr;
+	msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
+	msr.lo >>= 20;
+	printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
+	return ((msr.lo&0xf) == 5);
+}
+/* ***************************************************************************/
+/* **/
+/* *	pmChipsetInit*/
+/* **/
+/* *	Program ACPI LBAR and initialize ACPI registers.*/
+/* *  */
+/* **/
+/* *	Entry:*/
+/* *		None*/
+/* **/
+/* *	Exit:*/
+/* *		None*/
+/* **/
+/* *	Destroys:*/
+/* *		None*/
+/* **/
+/* ***************************************************************************/
+static void
+pmChipsetInit(void) {
+	unsigned long val = 0;
+	unsigned short port;
+
+	port =  (PMLogic_BASE + 0x010);
+	val =  0x0E00		; /*  1ms*/
+	outl(val, port);
+
+	/*  PM_WKXD*/
+	/*  Make sure bits[3:0]=0000b to clear the*/
+	/*  saved Sx state*/
+	port =  (PMLogic_BASE + 0x034);
+	val =  0x0A0		; /*  5ms*/
+	outl(val, port);
+	
+	/*  PM_WKD*/
+	port =  (PMLogic_BASE + 0x030);
+	outl(val, port);
+		
+	/*  PM_SED*/
+	port =  (PMLogic_BASE + 0x014);
+/* 	mov		eax, 0x057642	; 100ms, works*/
+	val =  0x04601		; /*  5ms*/
+	outl(val, port);
+	
+	/*  PM_SIDD*/
+	port =  (PMLogic_BASE + 0x020);
+/* 	mov		eax, 0x0AEC84	; 200ms, works*/
+	val =  0x08C02		; /*  10ms*/
+	outl(val, port);
+	
+	/*  GPIO24 OUT_AUX1 function is the external signal for 5535's vsb_working_aux*/
+	/*  which is de-asserted when 5535 enters Standby(S3 or S5) state.*/
+	/*  On Hawk, GPIO24 controls all voltage rails except Vmem and Vstandby.  This means*/
+	/*  GX2 will be fully de-powered if this control de-asserts in S3/S5.*/
+	/* */
+	/*  GPIO24 is setup in preChipsetInit for two reasons*/
+	/*  1. GPIO24 at reset defaults to disabled, since this signal is vsb_work_aux on*/
+	/*     Hawk it controls the FET's for all voltage rails except Vstanby & Vmem.*/
+	/*     BIOS needs to enable GPIO24 as OUT_AUX1 & OUTPUT_EN early so it is driven*/
+	/*     by 5535.*/
+	/*  2. Non-PM builds will require GPIO24 enabled for instant-off power button*/
+	/* */
+
+	/*  GPIO11 OUT_AUX1 function is the external signal for 5535's slp_clk_n which is asserted*/
+	/*  when 5535 enters Sleep(S1) state.*/
+	/*  On Hawk, GPIO11 is connected to control input of external clock generator*/
+	/*  for 14MHz, PCI, USB & LPC clocks.*/
+	/*  Programming of GPIO11 will be done by VSA PM code.  During VSA Init. BIOS writes*/
+	/*  PM Core Virual Register indicating if S1 Clocks should be On or Off. This is based*/
+	/*  on a Setup item.  We do not want to leave GPIO11 enabled because of a Hawk board*/
+	/*  problem.  With GPIO11 enabled in S3, something is back-driving GPIO11 causing it to*/
+	/*  float to 1.6-1.7V.*/
+
+}
+
+struct FLASH_DEVICE {
+	unsigned char fType;		/* Flash type: NOR or NAND */
+	unsigned char fInterface;	/* Flash interface: I/O or Memory */
+	unsigned long fMask;		/* Flash size/mask */
+};
+
+struct FLASH_DEVICE FlashInitTable[] = {
+	{ FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K },	/* CS0, or Flash Device 0 */
+	{ FLASH_TYPE_NONE, 0, 0 },	/* CS1, or Flash Device 1 */
+	{ FLASH_TYPE_NONE, 0, 0 },	/* CS2, or Flash Device 2 */
+	{ FLASH_TYPE_NONE, 0, 0 },	/* CS3, or Flash Device 3 */
+};
+
+#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+
+uint32_t FlashPort[] = {
+	MDD_LBAR_FLSH0,
+	MDD_LBAR_FLSH1,
+	MDD_LBAR_FLSH2,
+	MDD_LBAR_FLSH3
+	};
+
+/***************************************************************************
+ *
+ *	ChipsetFlashSetup
+ *
+ *	Flash LBARs need to be setup before VSA init so the PCI BARs have
+ *	correct size info.  Call this routine only if flash needs to be 
+ *	configured (don't call it if you want IDE).
+ *
+ *	Entry:
+ *	Exit:
+ *	Destroys:
+ *
+ **************************************************************************/
+static void ChipsetFlashSetup(void)
+{
+	msr_t msr;
+	int i;
+	int numEnabled = 0;
+
+	printk_debug("ChipsetFlashSetup++\n");
+	for (i = 0; i < FlashInitTableLen; i++) {
+		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
+			printk_debug("Enable CS%d\n", i);
+			/* we need to configure the memory/IO mask */
+			msr = rdmsr(FlashPort[i]);
+			msr.hi = 0;	/* start with the "enabled" bit clear */
+			if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
+				msr.hi |= 0x00000002;
+			else
+				msr.hi &= ~0x00000002;
+			if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
+				msr.hi |= 0x00000004;
+			else
+				msr.hi &= ~0x00000004;
+			msr.hi |= FlashInitTable[i].fMask;
+			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+			wrmsr(FlashPort[i], msr);
+
+			/* now write-enable the device */
+			msr = rdmsr(MDD_NORF_CNTRL);
+			msr.lo |= (1 << i);
+			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+			wrmsr(MDD_NORF_CNTRL, msr);
+
+			/* update the number enabled */
+			numEnabled++;
+		}
+	}
+
+	/* enable the flash */
+	if (0 != numEnabled) {
+		msr = rdmsr(MDD_PIN_OPT);
+		msr.lo &= ~1; /* PIN_OPT_IDE */
+		printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
+		wrmsr(MDD_PIN_OPT, msr);
+	}
+	printk_debug("ChipsetFlashSetup--\n");
+
+}
+
+
+ 
+/* ***************************************************************************/
+/* **/
+/* *	ChipsetGeodeLinkInit*/
+/* *	Handle chipset specific GeodeLink settings here. */
+/* *	Called from GeodeLink init code.*/
+/* **/
+/* *	Entry:*/
+/* *	Exit:*/
+/* *	Destroys: GS*/
+/* **/
+/* ***************************************************************************/
+static void 
+ChipsetGeodeLinkInit(void){
+	msr_t msr;
+	unsigned long msrnum;
+	unsigned long totalmem;
+
+	if (is_5536())
+		return;
+	/*  SWASIF for A1 DMA */
+	/*  Set all memory to  "just above systop" PCI so DMA will work*/
+	/*  check A1*/
+	msrnum = MSR_SB_GLCP + 0x17;
+	msr = rdmsr(msrnum);
+	if ((msr.lo&0xff) == 0x11)
+		return;
+
+	totalmem = sizeram() << 20 - 1;
+	totalmem >>= 12; 
+	totalmem = ~totalmem;
+	totalmem &= 0xfffff;
+	msr.lo = totalmem;
+	msr.hi = 0x20000000;				/*  Port 1 (PCI)*/
+	msrnum = MSR_SB_GLIU + 0x20;		/*  */;
+	wrmsr(msrnum, msr);
+}
+
+void
+chipsetinit (struct northbridge_amd_lx_config *nb){
+	msr_t msr;
+	struct msrinit *csi;
+	int i;
+	unsigned long msrnum;
+
+	outb( P80_CHIPSET_INIT, 0x80);
+	ChipsetGeodeLinkInit();
+#if 0
+	/* we hope NEVER to be in linuxbios when S3 resumes 
+	if (! IsS3Resume()) */
+	{
+		struct acpiinit *aci = acpi_init_table;
+		while (aci->ioreg){
+			if (aci->iolen == 2) {
+				outw(aci->regdata, aci->ioreg);
+				inw(aci->ioreg);
+			} else {
+				outl(aci->regdata, aci->ioreg);
+				inl(aci->ioreg);
+			}
+		}
+
+		pmChipsetInit();
+	}
+#endif
+
+
+	if (!is_5536()) {
+		/*  Setup USB. Need more details. #118.18*/
+		msrnum = MSR_SB_USB1 + 8;
+		msr.lo =  0x00012090;
+		msr.hi = 0;
+		wrmsr(msrnum, msr);
+		msrnum = MSR_SB_USB2 + 8;
+		wrmsr(msrnum, msr);
+	}
+	
+	/* set hd IRQ */
+	outl	(GPIOL_2_SET, GPIOL_INPUT_ENABLE);
+	outl	(GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
+
+	/*  Allow IO read and writes during a ATA DMA operation.*/
+	/*   This could be done in the HD rom but do it here for easier debugging.*/
+	
+	msrnum = ATA_SB_GLD_MSR_ERR;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~0x100;
+	wrmsr(msrnum, msr);
+
+	/*  Enable Post Primary IDE.*/
+	msrnum = GLPCI_SB_CTRL;
+	msr = rdmsr(msrnum);
+	msr.lo |=  GLPCI_CRTL_PPIDE_SET;
+	wrmsr(msrnum, msr);
+
+
+	/*  Set up Master Configuration Register*/
+	/*  If 5536, use same master config settings as 5535, except for OHCI MSRs*/
+	if (is_5536()) 
+		i = 2;
+	else
+		i = 0;
+
+	csi = &SB_MASTER_CONF_TABLE[i];
+	for(; csi->msrnum; csi++){
+		msr.lo = csi->msr.lo;
+		msr.hi = csi->msr.hi;
+		wrmsr(csi->msrnum, msr); // MSR - see table above
+	}
+
+
+	/*  Flash Setup*/
+	printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
+	if (nb->setupflash)
+		ChipsetFlashSetup();
+
+
+
+	/* */
+	/*  Set up Hardware Clock Gating*/
+	/* */
+	/* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
+	{
+		if (is_5536())
+			csi = CS5536_CLOCK_GATING_TABLE;
+		else
+			csi = CS5535_CLOCK_GATING_TABLE;
+
+		for(; csi->msrnum; csi++){
+			msr.lo = csi->msr.lo;
+			msr.hi = csi->msr.hi;
+			wrmsr(csi->msrnum, msr);	// MSR - see table above
+		}
+	}
+
+}
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
new file mode 100644
index 0000000000..4e0da1789d
--- /dev/null
+++ b/src/northbridge/amd/lx/grphinit.c
@@ -0,0 +1,43 @@
+#include <arch/io.h>
+#include <stdint.h>
+#include <cpu/amd/vr.h>
+ 
+#define VIDEO_MB	8					// MB of video memory
+
+/*
+ * Write to a Virtual Register
+ * AX = Class/Index
+ * CX = data to write
+ */
+void vrWrite(uint16_t wClassIndex, uint16_t wData)
+{
+	outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+	outw(wData, VRC_DATA);
+}
+
+ /*
+ * Read from a Virtual Register
+ * AX = Class/Index
+ * Returns a 16-bit word of data
+ */
+uint16_t vrRead(uint16_t wClassIndex)
+{
+	uint16_t wData;
+	outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX);
+	wData = inw(VRC_DATA);
+	return wData;
+}
+
+/*
+ * This function mirrors the Graphics_Init routine in GeodeROM.
+ */
+void graphics_init(void)
+{
+	/* SoftVG initialization */
+
+	/* Call SoftVG with the main configuration parameters. */
+	/* NOTE: SoftVG expects the memory size to be given in 512 KB pages */
+	vrWrite((VRC_VG <<  8) + VG_MEM_SIZE, 0x0100 | (VIDEO_MB * 2));
+}
+
+
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
new file mode 100644
index 0000000000..2de9afc7b6
--- /dev/null
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -0,0 +1,480 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "northbridge.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/amd/vr.h>
+#define VIDEO_MB 8
+
+extern void graphics_init(void);
+
+#define NORTHBRIDGE_FILE "northbridge.c"
+
+/* todo: add a resource record. We don't do this here because this may be called when 
+  * very little of the platform is actually working.
+  */
+int
+sizeram(void)
+{
+	msr_t msr;
+	int sizem = 0;
+	unsigned short dimm;
+
+	msr = rdmsr(0x20000018);
+	printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+
+	/* dimm 0 */
+	dimm = msr.hi;
+	/* installed? */
+	if ((dimm & 7) != 7)
+		sizem = (1 << ((dimm >> 12)-1)) * 8;
+
+
+	/* dimm 1*/
+	dimm = msr.hi >> 16;
+	/* installed? */
+	if ((dimm & 7) != 7)
+		sizem += (1 << ((dimm >> 12)-1)) * 8;
+
+	printk_debug("sizeram: sizem 0x%x\n", sizem);
+	return sizem;
+}
+
+
+/* here is programming for the various MSRs.*/
+#define IM_QWAIT 0x100000
+
+#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
+#define DMCF_SERIAL_LOAD_MISSES  (2) /* enabled */
+
+/* these are the 8-bit attributes for controlling RCONF registers */
+#define CACHE_DISABLE (1<<0)
+#define WRITE_ALLOCATE (1<<1)
+#define WRITE_PROTECT (1<<2)
+#define WRITE_THROUGH (1<<3)
+#define WRITE_COMBINE (1<<4)
+#define WRITE_SERIALIZE (1<<5)
+
+/* ram has none of this stuff */
+#define RAM_PROPERTIES (0)
+#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
+#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
+#define MSR_WS_CD_DEFAULT (0x21212121)
+
+/* 1810-1817 give you 8 registers with which to program protection regions */
+/* the are region configuration range registers, or RRCF */
+/* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
+/* so no left-shift needed for top or base */
+#define RRCF_LOW(base,properties) (base|(1<<8)|properties)
+#define RRCF_LOW_CD(base)	RRCF_LOW(base, CACHE_DISABLE)
+
+/* build initializer for P2D MSR */
+#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
+#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
+#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
+#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
+#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
+#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
+#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
+
+
+
+struct msr_defaults {
+	int msr_no;
+	msr_t msr;
+} msr_defaults [] = {
+	{0x1700, {.hi = 0, .lo = IM_QWAIT}},
+	{0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
+	/* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
+	/* for 180a, for now, we assume VSM will configure it */
+	/* 180b is left at reset value,a0000-bffff is non-cacheable */
+	/* 180c, c0000-dffff is set to write serialize and non-cachable */
+	/* oops, 180c will be set by cpu bug handling in cpubug.c */
+	//{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
+	/* 180d is left at default, e0000-fffff is non-cached */
+
+	/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
+	/* we will not set 0x180f, the DMM,yet */
+	//{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
+	//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
+	//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
+	//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
+	/* now for GLPCI routing */
+	/* GLIU0 */
+	P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
+	P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
+	P2D_SC(0x1000002c, 0x1, 0x0, 0x0,  0xff03, 0xC0000),
+	/* GLIU1 */
+	P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
+	P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
+	P2D_SC(0x4000002e, 0x1, 0x0, 0x0,  0xff03, 0xC0000), // GX3 0x4000002d -> 0x4000002e
+	{0}
+};
+
+/* note that dev is NOT used -- yet */
+static void irq_init_steering(struct device *dev, uint16_t irq_map) {
+	/* Set up IRQ steering */
+	uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+
+	printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map);
+
+	/* The IRQ steering values (in hex) are effectively dcba, where:
+	 *    <a> represents the IRQ for INTA, 
+	 *    <b> represents the IRQ for INTB,
+	 *    <c> represents the IRQ for INTC, and
+	 *    <d> represents the IRQ for INTD.
+	 * Thus, a value of irq_map = 0xAA5B translates to:
+	 *    INTA = IRQB (IRQ 11)
+	 *    INTB = IRQ5 (IRQ 5)
+	 *    INTC = IRQA (IRQ 10)
+	 *    INTD = IRQA (IRQ 10)
+	 */
+	outl(pciAddr & ~3, 0xCF8);
+	outl(irq_map,      0xCFC);
+}
+
+
+/*
+ * setup_lx_cache
+ *
+ * Returns the amount of memory (in KB) available to the system.  This is the 
+ * total amount of memory less the amount of memory reserved for SMM use.
+ *
+ */ 
+static int
+setup_lx_cache(void)
+{
+	msr_t msr;
+	unsigned long long val;
+	int sizekbytes, sizereg;
+
+	sizekbytes = sizeram() * 1024;
+	printk_debug("setup_lx_cache: enable for %d KB\n", sizekbytes);
+	/* build up the rconf word. */
+	/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
+	/* set romrp */
+	val = ((unsigned long long) ROM_PROPERTIES) << 56;
+	/* make rom base useful for 1M roms */
+	/* Flash base address -- sized for 1M for now*/
+	val |= ((unsigned long long) 0xfff00)<<36;
+	/* set the devrp properties */
+	val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
+	/* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
+	/* yank off memory for the SMM handler */
+	sizekbytes -= SMM_SIZE;
+	sizereg = sizekbytes;
+	sizereg *= 1024;	// convert to bytes
+	sizereg >>= 12;
+	sizereg <<= 8;
+	val |= sizereg;
+	val |= RAM_PROPERTIES;
+	msr.lo = val;
+	msr.hi = (val >> 32);
+	printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
+	wrmsr(CPU_RCONF_DEFAULT, msr);
+
+	enable_cache();
+	wbinvd();
+	return sizekbytes;
+}
+
+/* we have to do this here. We have not found a nicer way to do it */
+void
+setup_lx(void)
+{
+
+	unsigned long tmp, tmp2;
+	msr_t msr;
+	unsigned long size_kb, membytes;
+
+	size_kb = setup_lx_cache();
+
+	membytes = size_kb * 1024;
+	/* NOTE! setup_lx_cache returns the SIZE OF RAM - RAMADJUST!
+	  * so it is safe to use. You should NOT at this point call 	
+	  * sizeram() directly. 
+	  */
+
+	/* we need to set 0x10000028 and 0x40000029 */
+	/*
+	 * These two descriptors cover the range from 1 MB (0x100000) to 
+	 * SYSTOP (a.k.a. TOM, or Top of Memory)
+	 */
+
+#if 0
+	/* This has already been done elsewhere */
+	printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
+	msr.hi = 0x20000000 | membytes>>24;
+	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
+	wrmsr(0x10000028, msr);
+	msr.hi = 0x20000000 | membytes>>24;
+	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
+	wrmsr(0x40000029, msr);
+#endif
+#if 0
+	msr = rdmsr(0x10000028);
+	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+	msr = rdmsr(0x40000029);
+	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
+#endif
+#if 1
+	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
+	/* calculate the OFFSET field */
+	tmp = membytes - SMM_OFFSET;
+	tmp >>= 12;
+	tmp <<= 8;
+	tmp |= 0x20000000;
+	tmp |= (SMM_OFFSET >> 24);
+
+	/* calculate the PBASE and PMASK fields */
+	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
+	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
+	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+	msr.hi = tmp;
+	msr.lo = tmp2;
+	wrmsr(0x10000026, msr);
+#endif
+#if 0
+
+	msr.hi = 0x2cfbc040;
+	msr.lo = 0x400fffc0;
+	wrmsr(0x10000026, msr);
+	msr = rdmsr(0x10000026);
+	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+#endif
+#if 0
+	msr.hi = 0x22fffc02;
+	msr.lo = 0x10ffbf00;
+	wrmsr(0x1808, msr);
+	msr = rdmsr(0x1808);
+	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+#endif
+#if 0	// SDG - don't do this
+	/* now do the default MSR values */
+	for(i = 0; msr_defaults[i].msr_no; i++) {
+		msr_t msr;
+		wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);	// MSR - see table above
+		msr = rdmsr(msr_defaults[i].msr_no);
+		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
+	}
+#endif
+}
+
+static void enable_shadow(device_t dev)
+{
+	
+}
+
+static void northbridge_init(device_t dev) 
+{
+	struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
+	printk_debug("northbridge: %s()\n", __FUNCTION__);
+	
+	enable_shadow(dev);
+	irq_init_steering(dev, nb->irqmap);
+}
+
+static struct device_operations northbridge_operations = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = northbridge_init,
+	.enable           = 0,
+	.ops_pci          = 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+	.ops = &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_LX,
+};
+
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+
+static void pci_domain_read_resources(device_t dev)
+{
+        struct resource *resource;
+
+	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
+
+        /* Initialize the system wide io space constraints */
+        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
+        resource->limit = 0xffffUL;
+        resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+        /* Initialize the system wide memory resources constraints */
+        resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
+        resource->limit = 0xffffffffULL;
+        resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+        unsigned long basek, unsigned long sizek)
+{
+        struct resource *resource;
+
+        if (!sizek) {
+                return;
+        }
+        resource = new_resource(dev, index);
+        resource->base  = ((resource_t)basek) << 10;
+        resource->size  = ((resource_t)sizek) << 10;
+        resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+	struct resource **best_p = gp;
+	struct resource *best;
+	best = *best_p;
+	if (!best || (best->base > new->base)) {
+		best = new;
+	}
+	*best_p = best;
+}
+
+#if 0
+static uint32_t find_pci_tolm(struct bus *bus)
+{
+	struct resource *min;
+	uint32_t tolm;
+	min = 0;
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+	tolm = 0xffffffffUL;
+	if (min && tolm > min->base) {
+		tolm = min->base;
+	}
+	return tolm;
+}
+#endif
+#define FRAMEBUFFERK 4096
+
+static void pci_domain_set_resources(device_t dev)
+{
+#if 0
+	device_t mc_dev;
+        uint32_t pci_tolm;
+
+        pci_tolm = find_pci_tolm(&dev->link[0]);
+	mc_dev = dev->link[0].children;
+	if (mc_dev) {
+		unsigned int tomk, tolmk;
+		unsigned int ramreg = 0;
+		int i, idx;
+		unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
+		unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
+
+		for(i=0; i<0x20; i+= 0x10) {
+			unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
+			unsigned int mem_config = *mcreg;
+
+			if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
+				continue;
+			ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
+		}
+			
+		tomk = ramreg << 10;
+
+		/* Sort out the framebuffer size */
+		tomk -= FRAMEBUFFERK;
+		*bcdramtop = ((tomk << 10) - 1);
+		*mcgbaseadd = (tomk >> 9);
+
+		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+
+		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+
+		/* Compute the top of Low memory */
+		tolmk = pci_tolm >> 10;
+		if (tolmk >= tomk) {
+			/* The PCI hole does does not overlap the memory.
+			 */
+			tolmk = tomk;
+		}
+		/* Report the memory regions */
+		idx = 10;
+		ram_resource(dev, idx++, 0, tolmk);
+	}
+#endif
+	assign_resources(&dev->link[0]);
+}
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+        return max;
+}
+
+static struct device_operations pci_domain_ops = {
+        .read_resources   = pci_domain_read_resources,
+        .set_resources    = pci_domain_set_resources,
+        .enable_resources = enable_childrens_resources,
+        .init             = 0,
+        .scan_bus         = pci_domain_scan_bus,
+};  
+
+static void cpu_bus_init(device_t dev)
+{
+        initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+        .read_resources   = cpu_bus_noop,
+        .set_resources    = cpu_bus_noop,
+        .enable_resources = cpu_bus_noop,
+        .init             = cpu_bus_init,
+        .scan_bus         = 0,
+};
+
+void chipsetInit (void);
+
+static void enable_dev(struct device *dev)
+{
+	printk_debug("lx north: enable_dev\n");
+	void northbridgeinit(void);
+	void chipsetinit(struct northbridge_amd_lx_config *nb);
+	void setup_realmode_idt(void);
+	void do_vsmbios(void);
+        /* Set the operations if it is a special bus type */
+        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
+		extern void cpubug(void);
+		printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
+		/* cpubug MUST be called before setup_lx(), so we force the issue here */
+		northbridgeinit();
+		cpubug();	
+		chipsetinit(nb);
+		setup_lx();
+		/* do this here for now -- this chip really breaks our device model */
+		setup_realmode_idt();
+		do_vsmbios();
+		graphics_init();
+		dev->ops = &pci_domain_ops;
+		pci_set_method(dev);
+		ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE);
+        } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
+                dev->ops = &cpu_bus_ops;
+        }
+	printk_debug("lx north: end enable_dev\n");
+}
+
+struct chip_operations northbridge_amd_lx_ops = {
+	CHIP_NAME("AMD LX Northbridge")
+	.enable_dev = enable_dev, 
+};
diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h
new file mode 100644
index 0000000000..391fbf3177
--- /dev/null
+++ b/src/northbridge/amd/lx/northbridge.h
@@ -0,0 +1,6 @@
+#ifndef NORTHBRIDGE_AMD_LX_H
+#define NORTHBRIDGE_AMD_LX_H
+
+extern unsigned int lx_scan_root_bus(device_t root, unsigned int max);
+
+#endif /* NORTHBRIDGE_AMD_LX_H */
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
new file mode 100644
index 0000000000..08b8816610
--- /dev/null
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -0,0 +1,808 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "northbridge.h"
+#include <cpu/amd/lxdef.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/cache.h>
+
+/* put this here for now, we are not sure where it belongs */
+
+struct gliutable {
+	unsigned long desc_name;
+	unsigned short desc_type;
+	unsigned long hi, lo;
+};
+
+struct gliutable gliu0table[] = {
+	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},		/*  0-7FFFF to MC*/
+	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},		/*  80000-9ffff to Mc*/
+	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},	/*  C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
+	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU0_DMM,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
+	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},		/*  Catch and fix dynamicly.*/
+	{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
+	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+};
+
+
+struct gliutable gliu1table[] = {
+	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},	/*  0-7FFFF to MC*/
+	{.desc_name=MSR_GLIU1_BASE2,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/*  80000-9ffff to Mc*/
+	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03}, /*  C0000-Fffff split to MC and PCI (sub decode)*/
+	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},		/*  Cat0xc and fix dynamicly.*/
+	{.desc_name=MSR_GLIU1_DMM,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},			/*  Cat0xc and fix dynamicly.*/
+	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},			/*  Cat0xc and fix dynamicly.*/
+	{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
+	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0},	/*  FooGlue FPU 0xF0*/
+	{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+};
+
+struct gliutable *gliutables[]  = {gliu0table, gliu1table, 0};
+
+struct msrinit {
+	unsigned long msrnum;
+	msr_t msr;
+};
+
+struct msrinit ClockGatingDefault [] = {
+	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
+			/*  MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142*/
+	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
+	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
+	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},			/*  lotus #77.163*/
+	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
+	/*{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},*/ //GX3 
+	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
+	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
+	/*{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},	*/		/* Always on*/ //GX3
+	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+};
+	/*  All On*/
+struct msrinit ClockGatingAllOn[] = {
+	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
+	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0FFFFFFFF}},
+	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
+	{VG_GLD_MSR_PM,		{.hi=0x00, .lo=0x00}},
+	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x000000001}},
+	/*{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0FFFFFFFF}}, */ //GX3
+	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
+	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
+	/*{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}}, */ //GX3
+ 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+};
+
+	/*  Performance*/
+struct msrinit ClockGatingPerformance[] = {
+	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/*  lotus #77.163*/
+	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
+	/*{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},	*/ //GX3
+	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
+	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+};
+/* */
+/*  SET GeodeLink PRIORITY*/
+/* */
+struct msrinit GeodeLinkPriorityTable [] = {
+	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},	/*  CPU Priority.*/
+	/*{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},*/ 	/*  DF Priority.*/		//GX3
+	{VG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0720}},	/*  VG Primary and Secondary Priority.*/
+	{GP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0010}},	/*  Graphics Priority.*/
+	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},	/*  GLPCI Priority + PID*/
+	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},	/*  GLCP Priority + PID*/
+	{VIP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},	/*  VIP PID*/
+	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},	/*  AES PID*/
+	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/*  END*/
+};
+
+/* do we have dmi or not? assume NO per AMD */
+int havedmi = 0;
+
+static void
+writeglmsr(struct gliutable *gl){
+	msr_t msr;
+
+	msr.lo = gl->lo;
+	msr.hi = gl->hi;
+	wrmsr(gl->desc_name, msr);	// MSR - see table above
+	printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+	/* they do this, so we do this */
+	msr = rdmsr(gl->desc_name);
+	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+}
+
+static void
+ShadowInit(struct gliutable *gl)
+{
+	msr_t msr;
+
+	msr = rdmsr(gl->desc_name);
+
+	if (msr.lo == 0) {
+		writeglmsr(gl); 
+	}
+}
+
+/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. 
+  * CLEAN ME UP
+   */
+/* yes, this duplicates later code, but it seems that is how they want it done. 
+  */
+extern int sizeram(void);
+static void
+SysmemInit(struct gliutable *gl)
+{
+	msr_t msr;
+	int sizembytes, sizebytes;
+
+	/* 
+	 * Figure out how much RAM is in the machine and alocate all to the 
+	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
+	 */
+	sizembytes = sizeram();
+	printk_debug("%s: enable for %dm bytes\n", __FUNCTION__, sizembytes);
+	sizebytes = sizembytes << 20;
+
+	sizebytes -= SMM_SIZE*1024 +1;
+
+	if (havedmi)
+		sizebytes -= DMM_SIZE * 1024 + 1;
+
+	sizebytes -= 1;
+	msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
+	/* set up sizebytes to fit into msr.lo */
+	sizebytes <<= 8; /* what? well, we want bits 23:12 in bits 31:20. */
+	sizebytes &= 0xfff00000;
+	sizebytes |= 0x100;
+	msr.lo = sizebytes;
+	wrmsr(gl->desc_name, msr);	// MSR - see table above
+	msr = rdmsr(gl->desc_name);
+	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, 
+				gl->desc_name, msr.hi, msr.lo);
+	
+}
+static void
+DMMGL0Init(struct gliutable *gl) {
+	msr_t msr;
+	int sizebytes = sizeram()<<20;
+	long offset;
+
+	if (! havedmi)
+		return;
+
+	printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
+
+	sizebytes -= DMM_SIZE*1024;
+	offset = sizebytes - DMM_OFFSET;
+	printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, offset);
+	offset >>= 12;
+	msr.hi = (gl->hi) | (offset << 8);
+	/* I don't think this is needed */
+	msr.hi &= 0xffffff00;
+	msr.hi |= (DMM_OFFSET >> 24);
+	msr.lo = DMM_OFFSET << 8;
+	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
+	
+	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	msr = rdmsr(gl->desc_name);
+	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+	
+}
+static void
+DMMGL1Init(struct gliutable *gl) {
+	msr_t msr;
+
+	if (! havedmi)
+		return;
+
+	printk_debug("%s:\n", __FUNCTION__ );
+
+	msr.hi = gl->hi;
+	/* I don't think this is needed */
+	msr.hi &= 0xffffff00;
+	msr.hi |= (DMM_OFFSET >> 24);
+	msr.lo = DMM_OFFSET << 8;
+	/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
+	printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __FUNCTION__);
+	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
+	
+	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	msr = rdmsr(gl->desc_name);
+	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+}
+static void
+SMMGL0Init(struct gliutable *gl) {
+	msr_t msr;
+	int sizebytes = sizeram()<<20;
+	long offset;
+
+	sizebytes -= SMM_SIZE*1024;
+
+	if (havedmi)
+		sizebytes -= DMM_SIZE * 1024;
+
+	printk_debug("%s: %d bytes\n", __FUNCTION__, sizebytes);
+
+	offset = sizebytes - SMM_OFFSET;
+	printk_debug("%s: offset is 0x%08x\n", __FUNCTION__, offset);
+	offset >>= 12;
+
+	msr.hi = offset << 8;
+	msr.hi |= SMM_OFFSET>>24;
+
+	msr.lo = SMM_OFFSET << 8;
+	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
+	
+	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	msr = rdmsr(gl->desc_name);
+	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+}
+static void
+SMMGL1Init(struct gliutable *gl) {
+	msr_t msr;
+	printk_debug("%s:\n", __FUNCTION__ );
+
+	msr.hi = gl->hi;
+	/* I don't think this is needed */
+	msr.hi &= 0xffffff00;
+	msr.hi |= (SMM_OFFSET >> 24);
+	msr.lo = SMM_OFFSET << 8;
+	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
+	
+	wrmsr(gl->desc_name, msr);	// MSR - See table above
+	msr = rdmsr(gl->desc_name);
+	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __FUNCTION__, gl->desc_name, msr.hi, msr.lo);
+}
+
+static void
+GLIUInit(struct gliutable *gl){
+
+	while (gl->desc_type != GL_END){
+		switch(gl->desc_type){
+		default: 
+			/* For Unknown types: Write then read MSR */
+			writeglmsr(gl);
+		case SC_SHADOW: /*  Check for a Shadow entry*/
+			ShadowInit(gl);
+			break;
+	
+		case R_SYSMEM: /*  check for a SYSMEM entry*/
+			SysmemInit(gl);
+			break;
+	
+		case BMO_DMM: /*  check for a DMM entry*/
+			DMMGL0Init(gl);
+			break;
+	
+		case BM_DMM	: /*  check for a DMM entry*/
+			DMMGL1Init(gl);
+			break;
+	
+		case BMO_SMM	: /*  check for a SMM entry*/
+			SMMGL0Init(gl);
+			break;
+	
+		case BM_SMM	: /*  check for a SMM entry*/
+			SMMGL1Init(gl);	
+			break;
+		}
+		gl++;
+	}
+
+}
+	/* ***************************************************************************/
+	/* **/
+	/* *	GLPCIInit*/
+	/* **/
+	/* *	Set up GLPCI settings for reads/write into memory*/
+	/* *	R0:  0-640KB,*/
+	/* *	R1:  1MB - Top of System Memory*/
+	/* *	R2: SMM Memory*/
+	/* *	R3: Framebuffer? - not set up yet*/
+	/* *	R4: ??*/
+	/* **/
+	/* *	Entry:*/
+	/* *	Exit:*/
+	/* *	Modified:*/
+	/* **/
+	/* ***************************************************************************/
+static void GLPCIInit(void){
+	struct gliutable *gl = 0;
+	int i;
+	msr_t msr;
+	int msrnum;
+
+	/* */
+	/*  R0 - GLPCI settings for Conventional Memory space.*/
+	/* */
+	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT		/*  640*/;
+	msr.lo =  0							/*  0*/;
+	msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
+	msrnum = GLPCI_RC0;
+	wrmsr(msrnum, msr);
+
+	/* */
+	/*  R1 - GLPCI settings for SysMem space.*/
+	/* */
+	/*  Get systop from GLIU0 SYSTOP Descriptor*/
+	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+		if (gliu0table[i].desc_type == R_SYSMEM) {
+			gl = &gliu0table[i];
+			break;
+		}
+	}
+	if (gl) {
+		unsigned long pah, pal;
+		msrnum = gl->desc_name;
+		msr = rdmsr(msrnum);
+		/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
+                 * translates to a base of 0x00100000 and top of 0xffbf0000
+                 * base of 1M and top of around 256M
+		 */
+		/* we have to create a page-aligned (4KB page) address for base and top */
+		/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
+		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
+		 */
+		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
+		/* we have the page address. Now make it a page-aligned address */
+		pah <<= 12;
+
+		pal = msr.lo << 12;
+		msr.hi =  pah;
+		msr.lo =  pal;
+		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
+		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		msrnum = GLPCI_RC1;
+		wrmsr(msrnum, msr);
+	}
+
+	/* */
+	/*  R2 - GLPCI settings for SMM space.*/
+	/* */
+	msr.hi =  ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
+	msr.lo =  (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
+	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
+	msrnum = GLPCI_RC2;
+	wrmsr(msrnum, msr);
+
+	/* this is done elsewhere already, but it does no harm to do it more than once */
+	/*  write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
+	msr.lo =  0x021212121								/*  cache disabled and write serialized*/;
+	msr.hi =  0x021212121								/*  cache disabled and write serialized*/;
+
+	msrnum = CPU_RCONF_A0_BF;
+	wrmsr(msrnum, msr);
+
+	msrnum = CPU_RCONF_C0_DF;
+	wrmsr(msrnum, msr);
+
+	msrnum = CPU_RCONF_E0_FF;
+	wrmsr(msrnum, msr);
+
+	/*  Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
+	msrnum = GLPCI_A0_BF;
+	msr.hi =  0x35353535;
+	msr.lo =  0x35353535;
+	wrmsr(msrnum, msr);
+
+	msrnum = GLPCI_C0_DF;
+	msr.hi =  0x35353535;
+	msr.lo =  0x35353535;
+	wrmsr(msrnum, msr);
+
+	msrnum = GLPCI_E0_FF;
+	msr.hi =  0x35353535;
+	msr.lo =  0x35353535;
+	wrmsr(msrnum, msr);
+
+	/*  Set WSREQ*/
+	msrnum = CPU_DM_CONFIG0;
+	msr = rdmsr(msrnum);
+	msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
+	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT	;	/*  reduce to 1 for safe mode.*/
+	wrmsr(msrnum, msr);
+
+	/* we are ignoring the 5530 case for now, and perhaps forever. */
+
+	/* */
+	/* 5535 NB Init*/
+	/* */	
+	msrnum = GLPCI_ARB;
+	msr = rdmsr(msrnum);
+	msr.hi |=  GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
+	msr.lo |=  GLPCI_ARB_LOWER_IIE_SET;
+	wrmsr(msrnum, msr);
+
+
+	msrnum = GLPCI_CTRL;
+	msr = rdmsr(msrnum);
+
+	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/*   (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/
+	msr.lo |=  GLPCI_CTRL_LOWER_LDE_SET;
+
+	msr.lo &=  ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
+	msr.lo |=  0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
+
+	msr.lo &=  ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
+	msr.lo |=  0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
+	
+	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
+	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
+	
+	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
+	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
+	
+	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
+	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
+	
+	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
+	msr.hi |=  0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
+	
+	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
+	msr.hi |=  0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
+	wrmsr(msrnum, msr);
+
+
+	/*  Set GLPCI Latency Timer.*/
+	msrnum = GLPCI_CTRL;
+	msr = rdmsr(msrnum);
+	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/*  Change once 1.x is gone.*/
+	wrmsr(msrnum, msr);
+
+	/*  GLPCI_SPARE*/
+	msrnum = GLPCI_SPARE;
+	msr = rdmsr(msrnum);
+	msr.lo &=  ~ 0x7;
+	msr.lo |=  GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
+	wrmsr(msrnum, msr);
+
+}
+
+
+
+	/* ***************************************************************************/
+	/* **/
+	/* *	ClockGatingInit*/
+	/* **/
+	/* *	Enable Clock Gating.*/
+	/* **/
+	/* *	Entry:*/
+	/* *	Exit:*/
+	/* *	Modified:*/
+	/* **/
+	/* ***************************************************************************/
+static void 
+ClockGatingInit (void){
+	msr_t msr;
+	struct msrinit *gating = ClockGatingDefault;
+	int i;
+
+#if 0
+	mov	cx, TOKEN_CLK_GATE
+	NOSTACK	bx, GetNVRAMValueBX
+	cmp	al, TVALUE_CG_OFF
+	je	gatingdone
+	
+	cmp	al, TVALUE_CG_DEFAULT
+	jb	allon
+	ja	performance
+	lea	si, ClockGatingDefault
+	jmp	nextdevice
+
+allon:
+	lea	si, ClockGatingAllOn
+	jmp	nextdevice
+
+performance:
+	lea	si, ClockGatingPerformance
+#endif
+
+	for(i = 0; gating->msrnum != 0xffffffff; i++) {
+		msr = rdmsr(gating->msrnum);
+		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, gating->msrnum, msr.hi, msr.lo);
+		msr.hi |= gating->msr.hi;
+		msr.lo |= gating->msr.lo;
+		printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __FUNCTION__, 
+			gating->msrnum, msr.hi, msr.lo);
+		wrmsr(gating->msrnum, msr);	// MSR - See the table above
+		gating +=1;
+	}
+
+}
+
+static void 
+GeodeLinkPriority(void){
+	msr_t msr;
+	struct msrinit *prio = GeodeLinkPriorityTable;
+	int i;
+
+	for(i = 0; prio->msrnum != 0xffffffff; i++) {
+		msr = rdmsr(prio->msrnum);
+		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __FUNCTION__, prio->msrnum, msr.hi, msr.lo);
+		msr.hi |= prio->msr.hi;
+		msr.lo &= ~0xfff;
+		msr.lo |= prio->msr.lo;
+		printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __FUNCTION__, 
+			prio->msrnum, msr.hi, msr.lo);
+		wrmsr(prio->msrnum, msr);	// MSR - See the table above
+		prio +=1;
+	}
+}
+
+
+	
+/*
+ *	Get the GLIU0 shadow register settings
+ *	If the setShadow function is used then all shadow descriptors
+ *	  will stay sync'ed.
+ */
+static uint64_t getShadow(void)
+{
+	msr_t msr;
+	msr = rdmsr(MSR_GLIU0_SHADOW);
+	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
+}
+
+
+/*
+ *	Set the cache RConf registers for the memory hole.
+ *	Keeps all cache shadow descriptors sync'ed.
+ *	This is part of the PCI lockup solution
+ *	Entry: EDX:EAX is the shadow settings
+ */
+static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
+{
+	// ok this is whacky bit translation time.
+	int bit;
+	uint8_t shadowByte;
+	msr_t msr;
+	shadowByte = (uint8_t) (shadowLo >> 16);
+
+	// load up D000 settings in edx.
+	for (bit = 8; (bit > 4); bit--) {
+		msr.hi <<= 8;
+		msr.hi |= 1;						// cache disable PCI/Shadow memory
+		if (shadowByte && (1 << bit))
+			msr.hi |= 0x20;					// write serialize PCI memory
+	}
+
+	// load up C000 settings in eax.
+	for ( ; bit; bit--) {
+		msr.lo <<= 8;
+		msr.lo |= 1;						// cache disable PCI/Shadow memory
+		if (shadowByte && (1 << bit))
+			msr.lo |= 0x20;					// write serialize PCI memory
+	}
+
+	wrmsr(CPU_RCONF_C0_DF, msr);
+
+	shadowByte = (uint8_t) (shadowLo >> 24);
+
+	// load up F000 settings in edx.
+	for (bit = 8; (bit > 4); bit--) {
+		msr.hi <<= 8;
+		msr.hi |= 1;						// cache disable PCI/Shadow memory
+		if (shadowByte && (1 << bit))
+			msr.hi |= 0x20;					// write serialize PCI memory
+	}
+
+	// load up E000 settings in eax.
+	for ( ; bit; bit--) {
+		msr.lo <<= 8;
+		msr.lo |= 1;						// cache disable PCI/Shadow memory
+		if (shadowByte && (1 << bit))
+			msr.lo |= 0x20;					// write serialize PCI memory
+	}
+
+	wrmsr(CPU_RCONF_E0_FF, msr);
+}
+
+
+/*
+ *	Set the GLPCI registers for the memory hole.
+ *	Keeps all cache shadow descriptors sync'ed.
+ *	Entry: EDX:EAX is the shadow settings
+ */
+static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
+{
+	msr_t msr;
+	
+// Set the Enable Register.
+
+	msr = rdmsr(GLPCI_REN);
+	msr.lo &= 0xFFFF00FF;
+	msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
+	wrmsr(GLPCI_REN, msr);
+}
+
+
+/*
+ *	Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
+ *	Keeps all shadow descriptors sync'ed.
+ *	Entry: EDX:EAX is the shadow settings
+ */
+static void setShadow(uint64_t shadowSettings)
+{
+	int i;
+	msr_t msr;
+	struct gliutable* pTable;
+	uint32_t shadowLo, shadowHi;
+
+	shadowLo = (uint32_t) shadowSettings;
+	shadowHi = (uint32_t) (shadowSettings >> 32);
+
+	setShadowRCONF(shadowHi, shadowLo);
+	setShadowGLPCI(shadowHi, shadowLo);
+
+	for(i = 0; gliutables[i]; i++) {
+		for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {
+			if (pTable->desc_type == SC_SHADOW) {
+
+				msr = rdmsr(pTable->desc_name);
+				msr.lo = (uint32_t) shadowSettings;
+				msr.hi &= 0xFFFF0000;		// maintain PDID in upper EDX
+				msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
+				wrmsr(pTable->desc_name, msr);	// MSR - See the table above
+
+			}
+		}
+	}
+}
+
+/**************************************************************************
+ *
+ *	shadowRom
+ *
+ *	Set up a stack for ease of further testing
+ *
+ *	Entry:
+ *	Exit:
+ *	Destroys:
+ *
+ **************************************************************************/
+static void 
+shadowRom(void)
+{
+	uint64_t shadowSettings = getShadow();
+	shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL;	// Disable read & writes
+	shadowSettings |= (uint64_t) 0x00000000F0000000ULL;	// Enable reads for F0000-FFFFF
+	setShadow(shadowSettings);
+}
+
+
+
+/***************************************************************************
+ *
+ * RCONFInit
+ *	  Set up RCONF_DEFAULT and any other RCONF registers needed
+ *
+ *  DEVRC_RCONF_DEFAULT:
+ *  ROMRC(63:56) = 04h	 ; write protect ROMBASE
+ *  ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
+ *  DEVRC(35:28) =  39h	 ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
+ *  SYSTOP(27:8) = top of system memory
+ *  SYSRC(7:0) = 00h 		 ; writeback, can set to 08h to make writethrough 
+ *
+ ***************************************************************************/
+#define SYSMEM_RCONF_WRITETHROUGH 8
+#define DEVRC_RCONF_DEFAULT 0x21
+#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
+#define ROMRC_RCONF_DEFAULT 0x25
+
+static void
+RCONFInit(void)
+{
+	struct gliutable *gl = 0;
+	int i;
+	msr_t msr;
+	uint8_t SysMemCacheProp;
+	uint8_t RegionProp;
+
+	/* Locate SYSMEM entry in GLIU0table */
+	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+		if (gliu0table[i].desc_type == R_SYSMEM) {
+			gl = &gliu0table[i];
+			break;
+		}
+	}
+	if (gl == 0) {
+		post_code(0xCE);		/* POST_RCONFInitError */
+		while (1);
+	}
+
+// sysdescfound:	
+	/* found the descriptor... get its contents */
+	msr = rdmsr(gl->desc_name);
+
+	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the 
+	 * top 8 bits go into 0-7 of edx. 
+	 */
+	msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
+	msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
+	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	// 8
+	
+	// Set Default SYSMEM region properties
+	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	// 8 (or ~8)
+
+	// Set PCI space cache properties
+	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	// only need the bottom bits and lets clean the rest of edx
+	msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
+
+	// Set the ROMBASE. This is usually FFFC0000h
+	msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
+
+	// Set ROMBASE cache properties.
+	msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
+	
+	// now program RCONF_DEFAULT
+	wrmsr(CPU_RCONF_DEFAULT, msr);
+
+	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
+	// Set to match system memory cache properties.
+	msr = rdmsr(CPU_RCONF_DEFAULT);
+	SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
+	msr = rdmsr(CPU_RCONF_BYPASS);
+	msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
+	wrmsr(CPU_RCONF_BYPASS, msr);
+}
+
+
+/* ***************************************************************************/
+/* **/
+/* *	northBridgeInit*/
+/* **/
+/* *	Core Logic initialization:  Host bridge*/
+/* **/
+/* *	Entry:*/
+/* *	Exit:*/
+/* *	Modified:*/
+/* **/
+/* ***************************************************************************/
+
+void
+northbridgeinit(void)
+{
+	msr_t msr;
+	int i;
+	printk_debug("Enter %s\n", __FUNCTION__);
+
+	for(i = 0; gliutables[i]; i++)
+		GLIUInit(gliutables[i]);
+
+	GeodeLinkPriority();
+	
+	shadowRom();
+	
+	// GeodeROM ensures that the BIOS waits the required 1 second before 
+	// allowing anything to access PCI
+	// PCIDelay();
+	
+	RCONFInit();
+	
+	// The cacheInit function in GeodeROM tests cache and, among other things,
+	// makes sure all INVD instructions are treated as WBINVD.  We do this
+	// because we've found some programs which require this behavior.
+	// That subset of cacheInit() is implemented here:
+	msr = rdmsr(CPU_DM_CONFIG0);
+	msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
+	wrmsr(CPU_DM_CONFIG0, msr);
+	
+	/*  Now that the descriptor to memory is set up.*/
+	/*  The memory controller needs one read to synch its lines before it can be used.*/
+	i = *(int *) 0;
+
+	GLPCIInit();
+	ClockGatingInit();
+	__asm__("FINIT\n");
+	/* CPUBugsFix -- called elsewhere */
+	printk_debug("Exit %s\n", __FUNCTION__);
+}
+
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
new file mode 100644
index 0000000000..be92e9b90d
--- /dev/null
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -0,0 +1,85 @@
+#define POST_CODE(x) outb(0x80, x)
+
+static void pll_reset(void)
+{
+	msr_t msrGlcpSysRstpll;
+
+        msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
+	
+        print_debug("MSR GLCP_SYS_RSTPLL (");
+		print_debug_hex32(GLCP_SYS_RSTPLL);
+		print_debug(") value is: ");
+		print_debug_hex32(msrGlcpSysRstpll.hi);
+		print_debug(":");
+		print_debug_hex32(msrGlcpSysRstpll.lo);
+		print_debug("\n");
+	
+        msrGlcpSysRstpll.lo &= 0x80000000;
+
+	// If the "we've already been here" flag is set, don't reconfigure the pll
+        if ( !(msrGlcpSysRstpll.lo) )
+	{ // we haven't configured the PLL; do it now
+                POST_CODE(0x77);
+	
+               /*
+                *    64 - 32 	    |  31-0 
+                * 
+                *      (03FB)
+                * 0000 0011 1111 1011 | 1000 0000 1101 1110 0000 0000 1000 0001
+                * 
+                *      (039C)
+                * 0000 0011 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001
+                * 
+                *       (029C)
+                * 0000 0010 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001
+                * 
+                *       (02CB)
+                * 0000 0010 1100 1011 | 1000 0000 1101 1110 0000 0000 1000 0001
+                * 
+                * 00101		1			00101 		1 		| 100000	0		0		11011110 	0000 0000 1000 0001
+                * GLIUMULT	GLIUDIV		COREMULT	COREDIV	| SWFLAGS	(RO)	(RO)	HOLD_COUNT	
+                */
+
+                /* ### 02CB  ###
+                 * GLIUMULT = 6
+                 * GLIUDIV = 2
+                 * COREMULT = 6
+                 * COREDIV = 2
+                 * 
+                 * ### 03FB  ###
+                 * GLIUMULT = 8
+                 * GLIUDIV = 2
+                 * COREMULT = 30
+                 * COREDIV = 2
+                 * 
+                 * ### 039C  ###  bad... why?
+                 * GLIUMULT = 8
+                 * GLIUDIV = 0
+                 * COREMULT = 15
+                 * COREDIV = 0
+                 * 
+                 * ### 029C  ###  good...
+                 * GLIUMULT = 6
+                 * GLIUDIV = 0
+                 * COREMULT = 15
+                 * COREDIV = 0
+                 * 
+                 *  CLOCK = 33 MHz
+                 *
+                 */
+
+			/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2)  */
+			msrGlcpSysRstpll.hi = 0x0000029C;
+
+			/* Hold Count - how long we will sit in reset */
+			msrGlcpSysRstpll.lo = 0x00DE0000;
+
+			/* Use SWFLAGS to remember: "we've already been here"  */
+			msrGlcpSysRstpll.lo |= 0x80000000;
+
+			/* "reset the chip" value */
+			msrGlcpSysRstpll.lo |= 0x00000001;
+
+		wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
+	}
+}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
new file mode 100644
index 0000000000..7fd39ae22e
--- /dev/null
+++ b/src/northbridge/amd/lx/raminit.c
@@ -0,0 +1,143 @@
+#include <cpu/amd/lxdef.h>
+
+#if 0
+static void sdram_set_registers(const struct mem_controller *ctrl)
+{
+}
+
+#endif
+
+
+/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
+ * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
+static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+{
+	int i;
+	msr_t msr;
+
+	/* DRAM initialization sequence according to the documentation:
+	 * 1)  Initialize the following GLMC registers/bits based on Serial Presence Detect (SPD) values:
+	 *  — MSR 20000018h except REF_INT bits [23:8]
+   	 *   — MSR 20000019h
+   	 */
+   	
+   		// This is done by sdram_set_spd_registers()
+		/*WR_MSR   MC_CF07_DATA,   DIMMCONFIG, 0x05000040
+
+		;WR_MSR	MC_CF07_DATA,   DIMMCONFIG, 0x00000040		; MSR 20000018h except REF_INT bits [23:8]. REF_STAG value from DOCS*/
+		
+	/*
+	 * 0x18000100 : 0x696332A3
+	 * 
+	 * 		63 - 32 | 31                  15                0
+	 * xxxxxxx		| 0110 1001 0110 0011 0011 0010 1010 0011
+	 * 
+	 *  30:28 CAS latency
+	 * 
+	 * 010 - 2.0
+	 * 110 - 2.5
+	 *
+	 */
+
+	msr.hi = 0x18000100;
+	msr.lo = 0x696332A3;
+	wrmsr(MC_CF8F_DATA, msr);
+
+	/* 2)  Initialize the following GLMC registers:
+	 *	— MSR 2000001Ah[15:8] = C8h
+	 *	— MSR 20002004h[2] = 0, [0] = 1
+	 */
+	msr.hi = 0x00000000;
+	msr.lo = 0x130AD101;
+	wrmsr(MC_CF1017_DATA, msr);
+
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000001;
+	wrmsr(MC_GLD_MSR_PM, msr);
+
+	/* 3) Release MASK_CKE[1:0] (MSR 2000001Dh[9:8] = 11) */
+
+	msr.hi = 0x00000000;
+	msr.lo = 0x00001000;
+	wrmsr(MC_CFCLK_DBUG, msr);
+	
+	//print_debug("sdram_enable step 3\r\n");
+
+	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
+	 * why this is before EMRS and MRS ? */
+	 
+	for (i = 0; i < 19; i++) {
+		msr = rdmsr(MC_CF07_DATA);
+		msr.lo |=  (0x01 << 3);
+		wrmsr(MC_CF07_DATA, msr);
+		msr.lo &= ~(0x01 << 3);
+		wrmsr(MC_CF07_DATA, msr);
+	}
+
+
+	/* 5) Initialize REF_INT (MSR 20000018h[23:8]) to set refresh interval.	*/
+	msr.lo |= 0x2B00;
+	wrmsr(MC_CF07_DATA, msr);
+
+
+
+	/* set refresh staggering to 4 SDRAM clocks */
+	msr = rdmsr(0x20000018);
+	msr.lo &= ~(0x03 << 6);
+	msr.lo |=  (0x00 << 6);
+	wrmsr(0x20000018, msr);
+	//print_debug("sdram_enable step 5\r\n");
+
+
+	/* 6) Perform load-mode with MSR_BA = 01 (MSR 200000018h[29:28] = 01) 
+	 * to initialize DIMM Extended Mode register. 
+	 * Load-mode is performed by setting/clearing PROG_DRAM (MSR 200000018h[0]).
+	 */
+	msr.lo |=  ((0x01 << 28) | 0x01);
+	wrmsr(MC_CF07_DATA, msr);
+
+	msr.lo &= ~((0x01 << 28) | 0x01);
+	wrmsr(MC_CF07_DATA, msr);
+
+
+	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
+	 * it is documented in LX datasheet  */	
+	/* load Mode Register by set and clear PROG_DRAM */
+	msr = rdmsr(MC_CF07_DATA);
+	msr.lo |=  ((0x01 << 27) | 0x01);
+	wrmsr(MC_CF07_DATA, msr);
+	msr.lo &= ~((0x01 << 27) | 0x01);
+	wrmsr(MC_CF07_DATA, msr);
+	//print_debug("sdram_enable step 7\r\n");
+
+
+	/* 8. load Mode Register by set and clear PROG_DRAM */
+	msr = rdmsr(MC_CF07_DATA);
+	msr.lo |=  0x01;
+	wrmsr(MC_CF07_DATA, msr);
+	msr.lo &= ~0x01;
+	wrmsr(MC_CF07_DATA, msr);
+	//print_debug("sdram_enable step 8\r\n");
+
+	/* wait 200 SDCLKs */
+	for (i = 0; i < 200; i++)
+		outb(0xaa, 0x80);
+
+	/* load RDSYNC */
+	/*msr = rdmsr(0x2000001f);
+	msr.hi = 0x000ff310;
+	msr.lo = 0x00000000;
+	wrmsr(0x2000001f, msr);*/
+
+	/* set delay control */
+	msr = rdmsr(0x4c00000f);
+	msr.hi = 0x830d415a;
+	msr.lo = 0x8ea0ad6a;
+	wrmsr(0x4c00000f, msr);
+
+
+	print_debug("DRAM controller init done.\r\n");
+
+	/* DRAM working now?? */
+
+}
diff --git a/src/northbridge/amd/lx/raminit.h b/src/northbridge/amd/lx/raminit.h
new file mode 100644
index 0000000000..f13f53a09f
--- /dev/null
+++ b/src/northbridge/amd/lx/raminit.h
@@ -0,0 +1,10 @@
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#define DIMM_SOCKETS 2
+
+struct mem_controller {
+	uint16_t channel0[DIMM_SOCKETS];
+};
+
+#endif /* RAMINIT_H */