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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-14 16:36:09 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-20 07:17:32 +0100 |
| commit | af87020f0a3a813e03d3b059ae4284bbc8848ff1 (patch) | |
| tree | a50a2c9b1061ae264d71a289b70800b7a4b7a560 /src/northbridge/amd | |
| parent | 3787d5b36abb6735046a16e2195fb4057dacb07c (diff) | |
| download | coreboot-af87020f0a3a813e03d3b059ae4284bbc8848ff1.tar.xz | |
AGESA fam12: Fix MMCONF region
MMIO for non-posted region used hard-coded setting for 64 buses
while MSR programming was for 256 buses.
Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7812
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/agesa/family12/agesawrapper.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index f25e7379a9..d2aa3305f1 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -176,7 +176,7 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID) Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1; + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* @@ -187,7 +187,9 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Enable Non-Post Memory in CPU */ - PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80); + PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; + PciData = (PciData >> 8) & ~0xff; + PciData |= 0x80; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -198,7 +200,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID) /* Enable memory access */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); - PciData |= BIT1; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); |