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| author | Marc Jones <marc.jones@amd.com> | 2007-05-10 23:22:27 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2007-05-10 23:22:27 +0000 |
| commit | ddf845f620eb43d9ea2e8b0b265c321c6e797e6f (patch) | |
| tree | ae8b74aa6ab4df81ec7061db6ab8c1cb941e8b58 /src/northbridge/amd | |
| parent | 03625f4daf8bd92b8be64d795f8e46c01cc7468d (diff) | |
| download | coreboot-ddf845f620eb43d9ea2e8b0b265c321c6e797e6f.tar.xz | |
This patch cleans up and clarifies Geode source code comments.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/lx/northbridge.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 7f419e739e..4ad67006bb 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -127,6 +127,7 @@ int sizeram(void) int sizem = 0; unsigned short dimm; + /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ msr = rdmsr(MC_CF07_DATA); printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); @@ -134,14 +135,14 @@ int sizeram(void) dimm = msr.hi; /* installed? */ if ((dimm & 7) != 7) { - sizem = 4 << ((dimm >> 12) & 0x0F); + sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ } /* dimm 1 */ dimm = msr.hi >> 16; /* installed? */ if ((dimm & 7) != 7) { - sizem += 4 << ((dimm >> 12) & 0x0F); + sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ } printk_debug("sizeram: sizem 0x%xMB\n", sizem); |