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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-21 02:14:50 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-23 22:14:00 +0100 |
| commit | f1d807c5c603e9a77cf3ddd54e4aa3ceebcc3ae9 (patch) | |
| tree | 73654f7682d742f091fbb19db4c51c29f61551ea /src/northbridge/amd | |
| parent | 263522db97b5b16d2408fa11c5c158f88539bc8c (diff) | |
| download | coreboot-f1d807c5c603e9a77cf3ddd54e4aa3ceebcc3ae9.tar.xz | |
nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14148
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index da71816d6f..9a0d372528 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1555,7 +1555,6 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 Channel; - u8 Addl_Index = 0; u8 Receiver; u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; u32 Errors; @@ -1629,10 +1628,9 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, * This is essentially looping over each DIMM. */ for (; Receiver < 8; Receiver += 2) { - Addl_Index = (Receiver >> 1) * 3 + 0x10; dimm = (Receiver >> 1); - print_debug_dqs("\t\tTrainMaxRdLatency52: index ", Addl_Index, 2); + print_debug_dqs("\t\tTrainMaxRdLatency52: Receiver ", Receiver, 2); if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { continue; |