diff options
| author | Joseph Smith <joe@settoplinux.org> | 2010-04-09 11:10:25 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-09 11:10:25 +0000 |
| commit | 7488e049df9899dd7062b2ffe393b3e9a6f50dc5 (patch) | |
| tree | a226c1f16a9220abb947ba46d26570e065494aa5 /src/northbridge/amd | |
| parent | 853263b963b4cacb4f7fa3a7f2c68dcbd094f1d7 (diff) | |
| download | coreboot-7488e049df9899dd7062b2ffe393b3e9a6f50dc5.tar.xz | |
1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson
IP1000
Build and boot tested.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
The change to CAR reveiled a few more warnings in the ICH4 and i830 code,
I fixed them on the fly.
Checking this in because my last two commits broke Joseph's CAR patch. This
version fixes the issues.
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 5a82c51dc3..a668c9f1e0 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/stages.h> + //0: mean no debug info #define DQS_TRAIN_DEBUG 0 @@ -2091,7 +2093,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; } -static void copy_and_run_ap_code_in_car(unsigned ret_addr); + static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 |