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authorEric Biederman <ebiederm@xmission.com>2003-07-17 06:34:30 +0000
committerEric Biederman <ebiederm@xmission.com>2003-07-17 06:34:30 +0000
commitb03b33697d44fb4140922d47a4df1edd25a40a74 (patch)
tree6bea6160d290b3e26b817afb100575ae473db389 /src/northbridge/amd
parent2ec0020b3c703122cbe7c1b26ac3ad7ea8074464 (diff)
downloadcoreboot-b03b33697d44fb4140922d47a4df1edd25a40a74.tar.xz
- Update Config so we now have the proper number of cpus
- Remove some debugging code from auto.c - Update coeherent_ht.c so we get the proper broadcast routes. - Fix the dram probing code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c6
-rw-r--r--src/northbridge/amd/amdk8/raminit.c15
2 files changed, 12 insertions, 9 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 516f0fc6ae..5c11991646 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -526,8 +526,8 @@ static unsigned int generate_row(u8 node, u8 row, u8 maxnodes)
u32 ret=DEFAULT;
static const unsigned int rows_2p[2][2] = {
- { 0x00030101, 0x00010404 },
- { 0x00010404, 0x00030101 }
+ { 0x00050101, 0x00010404 },
+ { 0x00010404, 0x00050101 }
};
static const unsigned int rows_4p[4][4] = {
@@ -622,9 +622,11 @@ static void setup_remote_node(u8 node, u8 cpus)
uint32_t value;
uint8_t reg;
reg = pci_reg[i];
+#if 0
print_debug("copying reg: ");
print_debug_hex8(reg);
print_debug("\r\n");
+#endif
value = pci_read_config32(NODE_MP(0), reg);
pci_write_config32(NODE_MP(7), reg, value);
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index fac6e1adee..fd5956743f 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1123,20 +1123,21 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
{
#warning "FIXME this is hardcoded for one cpu"
unsigned node_id;
- unsigned link_id;
unsigned limit;
+ unsigned base;
node_id = 0;
- link_id = 0;
/* Route the addresses to node 0 */
limit = (limit_k << 2);
limit &= 0xffff0000;
limit -= 0x00010000;
- pci_write_config32(ctrl->f1, 0x44, limit | (0 << 7) | (link_id << 4) | (node_id << 0));
- pci_write_config32(ctrl->f1, 0x40, (base_k << 2) | (0 << 8) | (1<<1) | (1<<0));
+ base = (base_k << 2);
+ base &= 0xffff0000;
+ pci_write_config32(ctrl->f1, 0x44, limit | (0 << 8) | (node_id << 0));
+ pci_write_config32(ctrl->f1, 0x40, base | (0 << 8) | (1<<1) | (1<<0));
-#if 1
- pci_write_config32(PCI_DEV(0, 0x19, 1), 0x44, limit | (0 << 7) | (link_id << 4) | (node_id << 0));
- pci_write_config32(PCI_DEV(0, 0x19, 1), 0x40, (base_k << 2) | (0 << 8) | (1<<1) | (1<<0));
+#if 0
+ pci_write_config32(PCI_DEV(0, 0x19, 1), 0x44, limit | (0 << 8) | (1 << 4) | (node_id << 0));
+ pci_write_config32(PCI_DEV(0, 0x19, 1), 0x40, base | (0 << 8) | (1<<1) | (1<<0));
#endif
}