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| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-12-26 05:16:47 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2010-12-26 05:16:47 +0000 |
| commit | 3344743215acab0b7805592a7c52a9c93636b347 (patch) | |
| tree | e1d6732a24920b319f7ca6c94fff1d0f9ede1b54 /src/northbridge/amd | |
| parent | 1c6d4e605588c03edf4e7ab70056d7c075fc5bb1 (diff) | |
| download | coreboot-3344743215acab0b7805592a7c52a9c93636b347.tar.xz | |
Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 2b1db0d892..0f8013c057 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -29,8 +29,8 @@ int sizeram(void) unsigned short dimm; /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ - msr = rdmsr(0x20000018); - printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo); + msr = rdmsr(MC_CF07_DATA); + printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); /* dimm 0 */ dimm = msr.hi; |