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authorElyes HAOUAS <ehaouas@noos.fr>2019-06-26 20:17:50 +0200
committerMartin Roth <martinroth@google.com>2019-07-02 16:14:36 +0000
commit63f98f23045e072b0d07ecdd4cd50d01ad844df7 (patch)
treecd0cff2a76b8b44b9563de0cf63f2e8b831e9735 /src/northbridge/amd
parent7803e487bdd64ec0f1a8a17a483a4298d38bb77a (diff)
downloadcoreboot-63f98f23045e072b0d07ecdd4cd50d01ad844df7.tar.xz
src: Use CRx_TYPE type for CRx
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdmct/mct/mctdqs_d.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mctsrc.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mcttmrl.c2
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c5
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c7
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c4
6 files changed, 12 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 36ee3ab332..2e52a39619 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -278,7 +278,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
u8 dqsWrDelay_end;
u32 addr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0);
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 649c1c85c2..406547e0f8 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -129,7 +129,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
u32 index_reg;
u32 ch_start, ch_end, ch;
u32 msr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
u8 valid;
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index a78d42df85..6ec4d648d8 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -122,7 +122,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
u32 PatternBuffer[60]; // FIXME: why not 48 + 4
u32 Margin;
u32 addr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
u8 valid;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 34b13ea306..6b31294586 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -16,6 +16,7 @@
#include <inttypes.h>
#include <console/console.h>
+#include <cpu/x86/cr.h>
#include <string.h>
#include <arch/cpu.h>
#include <cpu/amd/msr.h>
@@ -405,7 +406,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
u32 dev;
u32 addr;
u8 valid;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
u32 index_reg;
uint32_t TestAddr;
@@ -1617,7 +1618,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
u8 _Wrap32Dis = 0, _SSE2 = 0;
u32 addr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
uint8_t dct;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index a6faf90e0c..032152c39d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -22,6 +22,7 @@
#include <arch/cpu.h>
#include <inttypes.h>
#include <console/console.h>
+#include <cpu/x86/cr.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
@@ -612,7 +613,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
u32 index_reg;
u32 ch_start, ch_end, ch;
msr_t msr;
- u32 cr4;
+ CRx_TYPE cr4;
uint32_t dword;
uint8_t dimm;
@@ -1186,7 +1187,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
u32 index_reg;
u32 ch_start, ch_end, ch;
u32 msr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
uint32_t dword;
@@ -1583,7 +1584,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
u32 index_reg;
u32 ch_start, ch_end;
u32 msr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
uint32_t dword;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
index e7b7883f13..ec9b8e4327 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -21,7 +21,7 @@
#include <inttypes.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
-
+#include <cpu/x86/cr.h>
#include "mct_d.h"
#include "mct_d_gcc.h"
@@ -119,7 +119,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
u32 PatternBuffer[60]; /* FIXME: why not 48 + 4 */
u32 Margin;
u32 addr;
- u32 cr4;
+ CRx_TYPE cr4;
u32 lo, hi;
u8 valid;