diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-09 02:47:51 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-24 19:27:43 +0100 |
| commit | 68130f506df5c77107ece8d71aa45b598be77b45 (patch) | |
| tree | fef16b57eadc6b180f97e4c5cc392d195d3cc239 /src/northbridge/amd | |
| parent | b174667534c327b8558ff04986a2c1a971b7f04e (diff) | |
| download | coreboot-68130f506df5c77107ece8d71aa45b598be77b45.tar.xz | |
amd/amdfam10: Control Fam15h cache partitioning via nvram
Add options to control cache partitioning and overall memory
performance via nvram.
Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 22 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 |
2 files changed, 32 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index ced64aa65e..600fdf8596 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1650,6 +1650,17 @@ static void detect_and_enable_probe_filter(device_t dev) { uint32_t dword; + uint8_t nvram; + uint8_t enable_probe_filter; + + /* Check to see if the probe filter is allowed */ + enable_probe_filter = 1; + if (get_option(&nvram, "probe_filter") == CB_SUCCESS) + enable_probe_filter = !!nvram; + + if (!enable_probe_filter) + return; + uint8_t fam15h = 0; uint8_t rev_gte_d = 0; uint8_t dual_node = 0; @@ -1810,6 +1821,17 @@ static void detect_and_enable_cache_partitioning(device_t dev) uint8_t i; uint32_t dword; + uint8_t nvram; + uint8_t enable_l3_cache_partitioning; + + /* Check to see if cache partitioning is allowed */ + enable_l3_cache_partitioning = 0; + if (get_option(&nvram, "l3_cache_partitioning") == CB_SUCCESS) + enable_l3_cache_partitioning = !!nvram; + + if (!enable_l3_cache_partitioning) + return; + if (is_fam15h()) { printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n"); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index aad813a056..a6cc70f9f5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5559,6 +5559,14 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, mct_ExtMCTConfig_Dx(pDCTstat); } else { /* Family 15h CPUs */ + uint8_t nvram; + uint8_t enable_experimental_memory_speed_boost; + + /* Check to see if cache partitioning is allowed */ + enable_experimental_memory_speed_boost = 0; + if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) + enable_experimental_memory_speed_boost = !!nvram; + val = 0x0ce00f00; /* FlushWrOnStpGnt = 0x0 */ val |= 0x10 << 2; /* MctWrLimit = 0x10 */ val |= 0x1; /* DctWrLimit = 0x1 */ @@ -5572,7 +5580,8 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ val |= (0x1 << 8); val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ - val |= (0x1 << 20); /* DblPrefEn = 0x1 */ + if (enable_experimental_memory_speed_boost) + val |= (0x1 << 20); /* DblPrefEn = 0x1 */ val |= (0x7 << 22); /* PrefFourConf = 0x7 */ val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */ |