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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-19 12:56:21 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:54:42 +0000 |
| commit | 727ac0d26395e4522e56ee988f1ef0097d982d51 (patch) | |
| tree | 5961761c98afe3ee4851a3e92aa1679d77c0d0c8 /src/northbridge/amd | |
| parent | a87a741b41ffb01612c7ef88d472d9092f707128 (diff) | |
| download | coreboot-727ac0d26395e4522e56ee988f1ef0097d982d51.tar.xz | |
AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID
PCI devices starting from 18 are processor configuration devices for each
node and are not a bus itself.
According to ACPI specification 6.3 section 6.1.5:
"... _HID object must be used to describe any device that will be
enumerated by OSPM. OSPM only enumerates a device when no bus enumerator
can detect the device ID. ... Use the _ADR object to describe devices
enumerated by bus enumerators other than OSPM."
PCI device 18 with its functions has a standard enumerator, which is PCI
enumerator so it needs a _ADR. Create a separate ACPI device for the
processor configuration space. This fixes the ACPI compliance problem
from CB:36318.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd')
6 files changed, 24 insertions, 6 deletions
diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index 06199a1b07..6e3bc934b1 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -18,13 +18,16 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* The internal GFX bridge */ Device(AGPB) { Name(_ADR, 0x00010000) diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 9a1fa9ed88..f679234e14 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index f74b31a080..3300db0c9c 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index c2b3aac4c5..f3d42fa4ad 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -17,7 +17,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Dev2 is also an external GFX bridge */ Device(PBR2) { Name(_ADR, 0x00020000) diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl index d54f985e90..761ff44399 100644 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index f74b31a080..3300db0c9c 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -18,7 +18,6 @@ External (TOM1) External (TOM2) Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ -Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Describe the Northbridge devices */ @@ -45,6 +44,10 @@ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ +Device(PCSD) { /* Processor configuration space devices */ + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ +} + /* Gpp 0 */ Device(PBR4) { Name(_ADR, 0x00020001) |