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authorTobias Diedrich <ranma+openocd@tdiedrich.de>2017-02-20 02:46:19 +0100
committerDuncan Laurie <dlaurie@chromium.org>2017-02-22 01:03:23 +0100
commitd8a2c1fb17b040dc81ca9da873bfcea41c1fe946 (patch)
tree2596c91ac33fddaae6392590f4662dd5ec7daaf2 /src/northbridge/amd
parentc248044b20d270d14cf460b04972b7ff741685d0 (diff)
downloadcoreboot-d8a2c1fb17b040dc81ca9da873bfcea41c1fe946.tar.xz
southbridge/amd: Add LPC bridge acpi path for Family14 and SB800
Adds the necessary plumbing for acpi_device_path() to find the LPC bridge on the AMD Family14 northbridge with an SB800 southbridge. This is necessary for TPM support since the acpi path to the LPC bridge (_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c (_SB.PCI0.LPCB). Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18402 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 15bb1aa209..b8d9c6fa6a 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -638,6 +638,14 @@ static void domain_enable_resources(device_t dev)
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
}
+static const char *domain_acpi_name(struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ return NULL;
+}
+
/* Bus related code */
static void cpu_bus_scan(struct device *dev)
@@ -813,6 +821,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = domain_enable_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
+ .acpi_name = domain_acpi_name,
};
static struct device_operations cpu_bus_ops = {