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authorEric Biederman <ebiederm@xmission.com>2004-11-18 22:38:08 +0000
committerEric Biederman <ebiederm@xmission.com>2004-11-18 22:38:08 +0000
commita9e632c2ac29c60872e7e4f9314263b34ce5031d (patch)
tree2a76647833896d68306553c548a65743c87b417e /src/northbridge/ibm
parentbec8acedf18b4d35f95b4a4c254eb925bd4d53bd (diff)
downloadcoreboot-a9e632c2ac29c60872e7e4f9314263b34ce5031d.tar.xz
- First stab at getting the ppc ports building and working.
- The sandpointx3+altimus has been consolidated into one directory for now. - Added support for having different versions of the pci access functions on a per bus basis if needed. Hopefully I have not broken something inadvertently. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/ibm')
-rw-r--r--src/northbridge/ibm/cpc710/Config.lb5
-rw-r--r--src/northbridge/ibm/cpc710/chip.h6
-rw-r--r--src/northbridge/ibm/cpc710/cpc710_northbridge.c103
3 files changed, 113 insertions, 1 deletions
diff --git a/src/northbridge/ibm/cpc710/Config.lb b/src/northbridge/ibm/cpc710/Config.lb
index 8d8a895bd7..054a4c3997 100644
--- a/src/northbridge/ibm/cpc710/Config.lb
+++ b/src/northbridge/ibm/cpc710/Config.lb
@@ -2,10 +2,13 @@
# Config file for IBM CPC710
#
+config chip.h
+
initobject cpc710.o
initobject cpc710_pci.o
#initobject cpc710_sdram.o
object cpc710.o
object cpc710_pci.o
-object cpc710_sdram.o
+#object cpc710_sdram.o
+driver cpc710_northbridge.o
diff --git a/src/northbridge/ibm/cpc710/chip.h b/src/northbridge/ibm/cpc710/chip.h
new file mode 100644
index 0000000000..e2b2ed5eaa
--- /dev/null
+++ b/src/northbridge/ibm/cpc710/chip.h
@@ -0,0 +1,6 @@
+
+struct northbridge_ibm_cpc710_config {
+ /* Nothing yet */
+};
+
+extern struct chip_operations northbridge_ibm_cpc710_ops;
diff --git a/src/northbridge/ibm/cpc710/cpc710_northbridge.c b/src/northbridge/ibm/cpc710/cpc710_northbridge.c
new file mode 100644
index 0000000000..2633dcd02c
--- /dev/null
+++ b/src/northbridge/ibm/cpc710/cpc710_northbridge.c
@@ -0,0 +1,103 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include "chip.h"
+
+static void pci_domain_read_resources(device_t dev)
+{
+ struct resource *resource;
+
+ /* Initialize the system wide io space constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ resource->base = 0;
+ resource->limit = 0xffffUL;
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+
+ /* Initialize the system wide memory resources constraints */
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ resource->base = 0x80000000ULL;
+ resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+ unsigned long basek, unsigned long sizek)
+{
+ struct resource *resource;
+
+ if (!sizek) {
+ return;
+ }
+ resource = new_resource(dev, index);
+ resource->base = ((resource_t)basek) << 10;
+ resource->size = ((resource_t)sizek) << 10;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ int idx;
+
+ /* Report the memory regions */
+ idx = 10;
+ ram_resource(dev, idx++, 0, 1024*1024); /* FIXME */
+
+ /* And assign the resources */
+ assign_resources(&dev->link[0]);
+}
+
+
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+ max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+ return max;
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = &pci_ppc_conf1,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+struct chip_operations northbridge_ibm_cpc710_ops = {
+ CHIP_NAME("CPC710")
+ .enable_dev = enable_dev,
+};