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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-28 21:05:26 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:28:48 +0200 |
| commit | 15279a9696c70b82c2223264a505da9122f9aa7b (patch) | |
| tree | 7038d85ab02e392f86a618c49f3db31e14d250f0 /src/northbridge/intel/e7505 | |
| parent | 585d1a0e7d0025e459a35b470572bcdbfff4e3c8 (diff) | |
| download | coreboot-15279a9696c70b82c2223264a505da9122f9aa7b.tar.xz | |
src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/e7505')
| -rw-r--r-- | src/northbridge/intel/e7505/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023c92..4a3e99379e 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the limit of the remap window */ remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, TOLM); |