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| author | Iru Cai <mytbk920423@gmail.com> | 2016-02-24 15:03:58 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-28 18:55:32 +0100 |
| commit | d7ee9dda708321f80161695714737b0f974509d3 (patch) | |
| tree | 3b939857d24f0261a0d498dc80bf93adea5e2550 /src/northbridge/intel/e7505 | |
| parent | 4351ace145c4069f9c93ca7541d6dfaf8300b53b (diff) | |
| download | coreboot-d7ee9dda708321f80161695714737b0f974509d3.tar.xz | |
northbridge/intel: add missing #include guards
I first found the missing of #include guards when I tried to include
both sandybridge/gma.h and sandybridge/sandybridge.h, but
sandybridge.h includes gma.h in it and gives a compile error.
Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/e7505')
| -rw-r--r-- | src/northbridge/intel/e7505/e7505.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 525dce8c79..9c9171d2bd 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * e7505.h: PCI configuration space for the Intel E7501 memory controller */ +#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H +#define NORTHBRIDGE_INTEL_E7505_E7505_H + /************ D0:F0 ************/ // Register offsets #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ @@ -78,3 +81,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ |