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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-08 22:36:38 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-13 13:16:26 +0000
commit55b7263ed825fa668f2a21d66cec57f01eccebe5 (patch)
tree897898f630c50ab42c8f0698a8d6b27866aa6b44 /src/northbridge/intel/e7505
parent3555389a8cdb4cb10deeafd2e116a387aa6ec5d4 (diff)
downloadcoreboot-55b7263ed825fa668f2a21d66cec57f01eccebe5.tar.xz
intel/e7505,i82801dx: Fix SMM_ASEG lock
In our codebase, this is only coupled with intel/e7505. The PCI registers reference here were for intel/i945. Also aseg_smm_lock() was previously not called. Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/e7505')
-rw-r--r--src/northbridge/intel/e7505/e7505.h2
-rw-r--r--src/northbridge/intel/e7505/memmap.c8
2 files changed, 10 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h
index b80d8a8a52..faf91440e8 100644
--- a/src/northbridge/intel/e7505/e7505.h
+++ b/src/northbridge/intel/e7505/e7505.h
@@ -42,6 +42,8 @@
#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */
#define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
#define CKDIS 0x8C /* Clock disable register, 8 bit */
+#define SMRAMC 0x9D
+#define ESMRAMC 0x9E
#define APSIZE 0xB4
#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */
#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index d45006566e..b954c6af74 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -35,6 +35,14 @@ void *cbmem_top(void)
return (void *)tolm;
}
+void northbridge_write_smram(u8 smram);
+
+void northbridge_write_smram(u8 smram)
+{
+ pci_devfn_t mch = PCI_DEV(0, 0, 0);
+ pci_write_config8(mch, SMRAMC, smram);
+}
+
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */