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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-04-19 19:57:01 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-05-27 13:54:47 +0200
commit70d92b9465b1edf646b25b89f1442f7107b5f1f6 (patch)
tree8d0a39990358f3fd92b00f0e790b7667ca90fd1c /src/northbridge/intel/e7505
parentef8bb9136e9371753e50cb15b334c9d0f5c70930 (diff)
downloadcoreboot-70d92b9465b1edf646b25b89f1442f7107b5f1f6.tar.xz
CBMEM: Clarify CBMEM_TOP_BACKUP function usage
The deprecated LATE_CBMEM_INIT function is renamed: set_top_of_ram -> set_late_cbmem_top Obscure term top_of_ram is replaced: backup_top_of_ram -> backup_top_of_low_cacheable get_top_of_ram -> restore_top_of_low_cacheable New function that always resolves to CBMEM top boundary, with or without SMM, is named restore_cbmem_top(). Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Diffstat (limited to 'src/northbridge/intel/e7505')
-rw-r--r--src/northbridge/intel/e7505/northbridge.c2
-rw-r--r--src/northbridge/intel/e7505/raminit.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 71b19f6cf2..f6e14d67f7 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -92,7 +92,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
- set_top_of_ram(tolmk * 1024);
+ set_late_cbmem_top(tolmk * 1024);
}
assign_resources(dev->link_list);
}
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 9adbca1a30..975a373433 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1892,10 +1892,10 @@ void e7505_mch_init(const struct mem_controller *memctrl)
sdram_enable(memctrl);
}
-unsigned long get_top_of_ram(void)
+uintptr_t restore_top_of_low_cacheable(void)
{
u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16;
- return (unsigned long) tolm;
+ return tolm;
}
/**