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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-03 10:51:34 +0300 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-11 01:29:35 +0200 |
| commit | 33e5df3f25b4594c008788625cd405d988fc6e6b (patch) | |
| tree | ddccf1263e8a71fe9d12202aa2a4c374c5a4e336 /src/northbridge/intel/e7505 | |
| parent | 52914323bf876342ab3497bfc527f139680d1612 (diff) | |
| download | coreboot-33e5df3f25b4594c008788625cd405d988fc6e6b.tar.xz | |
Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.
Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/e7505')
| -rw-r--r-- | src/northbridge/intel/e7505/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 6ee371f4aa..5fbc2e4e86 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -109,7 +109,7 @@ static struct device_operations pci_domain_ops = { .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci = &intel_pci_ops, - .ops_pci_bus = &pci_cf8_conf1, + .ops_pci_bus = pci_bus_default_ops, }; static void cpu_bus_init(device_t dev) |