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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-17 02:46:24 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:11:06 +0100 |
| commit | 5878bbd935c8cbd7c6d25ef72a5460f3262119e7 (patch) | |
| tree | 5a8500e6c3d5afbbdf2e54e51f9ef46ad3a4d6d0 /src/northbridge/intel/e7520/pciexp_porta.c | |
| parent | 61ed48c9233e0d74ef5c6847052662d075553691 (diff) | |
| download | coreboot-5878bbd935c8cbd7c6d25ef72a5460f3262119e7.tar.xz | |
Drop Intel E7520 and E7525 and related boards
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies
Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel/e7520/pciexp_porta.c')
| -rw-r--r-- | src/northbridge/intel/e7520/pciexp_porta.c | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c deleted file mode 100644 index f3639ad0c5..0000000000 --- a/src/northbridge/intel/e7520/pciexp_porta.c +++ /dev/null @@ -1,60 +0,0 @@ -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pciexp.h> -#include <arch/io.h> -#include "chip.h" -#include <reset.h> - -typedef struct northbridge_intel_e7520_config config_t; - -static void pcie_init(struct device *dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } - -} - -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) -{ - uint16_t val; - uint16_t ctl; - int flag = 0; - do { - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if((val & (1<<10) )&&(!flag)) { /* training error */ - ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag=1; - hard_reset(); - } - } while ( val & (3<<10) ); - return pciexp_scan_bridge(dev, max); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PA, -}; |