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author | York Yang <york.yang@intel.com> | 2015-01-05 10:04:45 -0700 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2015-01-31 23:09:26 +0100 |
commit | e1e11e63afab8e461ac7e6466c9a7f9f47a10702 (patch) | |
tree | 4f9587be74905d98c8f2ab071acbb8369613b687 /src/northbridge/intel/fsp_rangeley/chip.h | |
parent | 9cd155334baa28331f2cf2e6e7bf57c912d7a731 (diff) | |
download | coreboot-e1e11e63afab8e461ac7e6466c9a7f9f47a10702.tar.xz |
intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
by UPD input. Update UPD_DATA_REGION structure for matching up this
FSP change.
PcdCustomerRevision is a debugging aid that will be output to debug
message in FSP. When needed, it can be customized by BCT tool for tracking
BCT configurations.
Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley/chip.h')
-rw-r--r-- | src/northbridge/intel/fsp_rangeley/chip.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h index 80a22bf1ea..d3828c7764 100644 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ b/src/northbridge/intel/fsp_rangeley/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,6 +58,15 @@ struct northbridge_intel_fsp_rangeley_config { #define BIFURCATION_8_8 3 #define BIFURCATION_16 4 uint8_t Bifurcation; + + /* PCIe port de-emphasis control */ + #define DE_EMPHASIS_DEFAULT 0 + #define DE_EMPHASIS_MINUS_6_0_DB 1 + #define DE_EMPHASIS_MINUS_3_5_DB 2 + uint8_t PcdPcieRootPort1DeEmphasis; + uint8_t PcdPcieRootPort2DeEmphasis; + uint8_t PcdPcieRootPort3DeEmphasis; + uint8_t PcdPcieRootPort4DeEmphasis; }; #endif |