northbridge/intel: Add fsp_rangeley northbridge support

This adds the northbridge initialization pieces for Intel's Atom C2000
processor (Formerly Rangeley).  It is intended to be used with the Intel
Atom C2000 FSP and does not contain all of the pieces that would
otherwise be required for initialization.

Not currently supported:
S3 suspend/resume
CAR memory Migration (No early cbmem console)
SMM

Change-Id: I7665212c892d9a08ecf35d7be70d0afe5fd2c77b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6369
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

4 files changed, 299 insertions, 0 deletions

diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig
new file mode 100644
index 0000000000..82ecedaf7b
--- /dev/null
+++ b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config RANGELEY_FSP_SPECIFIC_OPTIONS
+	def_bool y
+	select PLATFORM_USES_FSP
+	select USE_GENERIC_FSP_CAR_INC
+	select FSP_USES_UPD
+	select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data
+
+config FSP_FILE
+	string
+	default "../intel/fsp/rangeley/FvFsp.bin"
+	help
+	  The path and filename of the Intel FSP binary for this platform.
+
+config FSP_LOC
+	hex
+	default 0xfff80000
+	help
+	  The location in CBFS that the FSP is located. This must match the
+	  value that is set in the FSP binary.  If the FSP needs to be moved,
+	  rebase the FSP with Intel's BCT (tool).
+
+	  The Rangeley FSP is built with a preferred base address of 0xFFF80000
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xfef00000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x4000
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc b/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc
new file mode 100644
index 0000000000..05620aedcc
--- /dev/null
+++ b/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-y += chipset_fsp_util.c
+romstage-y += chipset_fsp_util.c
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
new file mode 100644
index 0000000000..bd196a5059
--- /dev/null
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cpu/x86/stack.h>
+#include <console/console.h>
+#include <bootstate.h>
+#include <cbmem.h>
+#include <device/device.h>
+#include <southbridge/intel/fsp_rangeley/pci_devs.h>
+#include <drivers/intel/fsp/fsp_util.h>
+#include <fspvpd.h>
+#include <fspbootmode.h>
+#include <reset.h>
+#include "../chip.h"
+
+#ifdef __PRE_RAM__
+#include <southbridge/intel/fsp_rangeley/romstage.h>
+#endif
+
+#ifdef __PRE_RAM__
+
+/* Copy the default UPD region and settings to a buffer for modification */
+static void GetUpdDefaultFromFsp
+	(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
+{
+	VPD_DATA_REGION *VpdDataRgnPtr;
+	UPD_DATA_REGION *UpdDataRgnPtr;
+	VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset
+			+ FspInfo->ImageBase);
+	UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)
+			(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
+	memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+}
+
+typedef struct northbridge_intel_fsp_rangeley_config config_t;
+
+/**
+ * Update the UPD data based on values from devicetree.cb
+ *
+ * @param UpdData Pointer to the UPD Data structure
+ */
+static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
+{
+	ROMSTAGE_CONST struct device *dev;
+	ROMSTAGE_CONST config_t *config;
+	printk(BIOS_DEBUG, "Configure Default UPD Data\n");
+
+	dev = dev_find_slot(0, SOC_DEV_FUNC);
+	config = dev->chip_info;
+
+	/* Set SPD addresses */
+	if(config->SpdBaseAddress_0_0) {
+		UpdData->PcdSpdBaseAddress_0_0 = config->SpdBaseAddress_0_0;
+	}
+	if(config->SpdBaseAddress_0_1) {
+		UpdData->PcdSpdBaseAddress_0_1 = config->SpdBaseAddress_0_1;
+	}
+	if(config->SpdBaseAddress_1_0) {
+		UpdData->PcdSpdBaseAddress_1_0 = config->SpdBaseAddress_1_0;
+	}
+	if(config->SpdBaseAddress_1_1) {
+		UpdData->PcdSpdBaseAddress_1_1 = config->SpdBaseAddress_1_1;
+	}
+	if(config->EccSupport) {
+		UpdData->PcdEccSupport = config->EccSupport;
+	}
+	if(config->PrintDebugMessages) {
+		UpdData->PcdPrintDebugMessages = config->PrintDebugMessages;
+	}
+	if(config->Bifurcation) {
+		UpdData->PcdBifurcation = config->Bifurcation;
+	}
+	if(config->MemoryDown) {
+		UpdData->PcdMemoryDown = config->MemoryDown;
+	}
+
+	UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20;
+
+	if(config->MrcRmtCpgcExpLoopCntValue) {
+		UpdData->PcdMrcRmtCpgcExpLoopCntValue =
+				config->MrcRmtCpgcExpLoopCntValue;
+	}
+	if(config->MrcRmtCpgcNumBursts) {
+		UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts;
+	}
+#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT)
+	UpdData->PcdFastboot = UPD_ENABLE;
+#endif
+	/*
+	 * Loop through all the SOC devices in the devicetree
+	 *  enabling and disabling them as requested.
+	 */
+	for (; dev; dev = dev->sibling) {
+
+		if (dev->path.type != DEVICE_PATH_PCI)
+			continue;
+
+		switch (dev->path.pci.devfn) {
+			case GBE1_DEV_FUNC:
+			case GBE2_DEV_FUNC:
+			case GBE3_DEV_FUNC:
+			case GBE4_DEV_FUNC:
+				UpdData->PcdEnableLan |= dev->enabled;
+				printk(BIOS_DEBUG, "PcdEnableLan %d\n",
+						UpdData->PcdEnableLan);
+				break;
+			case SATA2_DEV_FUNC:
+				UpdData->PcdEnableSata2 = dev->enabled;
+				printk(BIOS_DEBUG, "PcdEnableSata2 %d\n",
+						UpdData->PcdEnableSata2);
+				break;
+			case SATA3_DEV_FUNC:
+				UpdData->PcdEnableSata3 = dev->enabled;
+				printk(BIOS_DEBUG, "PcdEnableSata3 %d\n",
+						UpdData->PcdEnableSata3);
+				break;
+			case IQAT_DEV_FUNC:
+				UpdData->PcdEnableIQAT |= dev->enabled;
+				printk(BIOS_DEBUG, "PcdEnableIQAT %d\n",
+					UpdData->PcdEnableIQAT);
+				break;
+			case USB2_DEV_FUNC:
+				UpdData->PcdEnableUsb20 = dev->enabled;
+				printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n",
+						UpdData->PcdEnableUsb20);
+				break;
+		}
+	}
+}
+
+/* Set up the Rangeley specific structures for the call into the FSP */
+void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
+		FSP_INFO_HEADER *fsp_ptr)
+{
+	FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr;
+
+	/* Initialize the UPD Data */
+	GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
+	ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
+	pFspInitParams->NvsBufferPtr = NULL;
+	pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+	/* Find the fastboot cache that was saved in the ROM */
+	pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
+
+	return;
+}
+
+/* The FSP returns here after the fsp_early_init call */
+void ChipsetFspReturnPoint(EFI_STATUS Status,
+		VOID *HobListPtr)
+{
+	if (Status == 0xFFFFFFFF) {
+		soft_reset();
+	}
+	romstage_main_continue(Status, HobListPtr);
+}
+
+#endif	/* __PRE_RAM__ */
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
new file mode 100644
index 0000000000..3057865b89
--- /dev/null
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CHIPSET_FSP_UTIL_H
+#define CHIPSET_FSP_UTIL_H
+
+#include <fsptypes.h>
+#include <fspfv.h>
+#include <fspffs.h>
+#include <fspapi.h>
+#include <fspplatform.h>
+#include <fspinfoheader.h>
+#include <fsphob.h>
+#include <fspvpd.h>
+
+#define FSP_RESERVE_MEMORY_SIZE	0x200000
+
+#define FSP_INFO_HEADER_GUID \
+  { \
+  0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
+  }
+
+#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
+  { \
+  0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0} \
+  }
+
+/*
+ *The FSP Image ID is different for each platform's FSP and
+ * can be used to verify that the right FSP binary is loaded.
+ * For the Rangeley FSP, the Image Id is "AVN-FSP0".
+ */
+#define FSP_IMAGE_ID_DWORD0 0x2d4e5641	/* 'AVN-' */
+#define FSP_IMAGE_ID_DWORD1 0x30505346	/* 'FSP0' */
+
+#endif /* CHIPSET_FSP_UTIL_H */