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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 18:37:28 +0100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-21 06:38:45 +0000 |
commit | c2c634a089fa990418c363e2ff2e5ff70bdd3580 (patch) | |
tree | 042e376cee473f72f143ed76768f50536ab323ef /src/northbridge/intel/fsp_rangeley/northbridge.h | |
parent | 298619f6d9adde49b4279c906b0d20a41f919a61 (diff) | |
download | coreboot-c2c634a089fa990418c363e2ff2e5ff70bdd3580.tar.xz |
nb/sb/cpu: Drop Intel Rangeley support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley/northbridge.h')
-rw-r--r-- | src/northbridge/intel/fsp_rangeley/northbridge.h | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h deleted file mode 100644 index fd5fa05a39..0000000000 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ - -#include <device/device.h> - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ - -/* SideBand B-UNIT */ -#define B_UNIT 3 - #define BNOCACHE 0x23 - #define BNOCACHECTL 0x24 - #define BMBOUND 0x25 - #define BMBOUND_HI 0x26 - #define BECREG 0x27 - #define BMISC 0x28 - #define BSMMRRL 0x2E - #define BSMMRRH 0x2F - #define BIMR0L 0x80 - #define BIMR0H 0x81 - #define BIMR0RAC 0x82 - #define BIMR0WAC 0x83 - -/* SideBand C-UNIT */ -#define C_UNIT 8 - -/* SideBand D-UNIT */ -#define D_UNIT 1 - -/* SideBand P-UNIT */ -#define P_UNIT 4 - -#ifndef __ASSEMBLER__ - -#define PCI_DEVICE_ID_RG_MIN 0x1F00 -#define PCI_DEVICE_ID_RG_MAX 0x1F0F -#define SKPAD 0xFC - -int bridge_silicon_revision(void); -void rangeley_late_initialization(void); -u32 sideband_read(int port, int reg); -void sideband_write(int port, int reg, long data); - -void northbridge_acpi_fill_ssdt_generator(struct device *device); - -#endif /* #ifndef __ASSEMBLER__ */ -#endif /* #ifndef __ACPI__ */ -#endif /* __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */ |