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author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-21 11:10:03 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2019-04-06 16:09:12 +0000 |
commit | bf0970e762a6611cef06af761bc2dec068d439bb (patch) | |
tree | 44d4854b7027794bc5a76b44a4e8fd07935cd60c /src/northbridge/intel/fsp_rangeley | |
parent | 161eafb0fb9563decbb953d5dccac4762b770e0c (diff) | |
download | coreboot-bf0970e762a6611cef06af761bc2dec068d439bb.tar.xz |
src: Use include <delay.h> when appropriate
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Diffstat (limited to 'src/northbridge/intel/fsp_rangeley')
-rw-r--r-- | src/northbridge/intel/fsp_rangeley/northbridge.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index edc623a33b..63f2068725 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <device/pci_ops.h> #include <stdint.h> -#include <delay.h> #include <cpu/intel/fsp_model_406dx/model_406dx.h> #include <device/device.h> #include <device/pci.h> |