diff options
| author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
| commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
| tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h | |
| parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) | |
| download | coreboot-3313a78e36da73f05da7402699f04909595a0c9d.tar.xz | |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h b/src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h deleted file mode 100644 index ac2efd6c8c..0000000000 --- a/src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ -#define _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* NB PCIe PEG slot */ -#define NB_PEG_DEV 0x01 -#define NB_PEG_FUNC 0 -# define NB_PEG_DEVFN PCI_DEVFN(NB_PEG_DEV, NB_PEG_FUNC) -#define PCIE_CTRL1_FUNC 1 -# define PCIE_CTRL1_DEVFN PCI_DEVFN(NB_PEG_DEV, PCIE_CTRL1_FUNC) -#define PCIE_CTRL2_FUNC 2 -# define PCIE_CTRL2_DEVFN PCI_DEVFN(NB_PEG_DEV, PCIE_CTRL2_FUNC) - -/* Onboard Graphics */ -#define GFX_DEV 0x02 -#define GFX_FUNC 0 -# define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) - -/* NB PCIe slot */ -#define NB_PCIE_DEV 0x06 -#define NB_PCIE_FUNC 0 -# define NB_PCIE_DEVFN PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_FUNC) - -#endif /* _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ */ |