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| author | Nico Huber <nico.huber@secunet.com> | 2017-01-19 16:28:18 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-04 23:04:06 +0100 |
| commit | 561bebfbaa55d5ab0656fbfc4866de88722d9618 (patch) | |
| tree | fb725cf6df5e7c1093523b57ed924046ad4d423e /src/northbridge/intel/gm45/Kconfig | |
| parent | 84394616dffac91bcf94423ed02b2877fc2d270f (diff) | |
| download | coreboot-561bebfbaa55d5ab0656fbfc4866de88722d9618.tar.xz | |
drivers/intel/gma/vbt: Add Kconfig symbol for SSC ref
The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.
The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz). The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.
Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/gm45/Kconfig')
| -rw-r--r-- | src/northbridge/intel/gm45/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 9a370d5fd0..ea6933d26e 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -24,6 +24,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI + select INTEL_GMA_SSC_ALTERNATE_REF select RELOCATABLE_RAMSTAGE config CBFS_SIZE |