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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-03 21:28:40 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-07 05:42:15 +0000
commitfe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 (patch)
treeb0e0c39376de50d41f3d6e21ed4b3aa47262d897 /src/northbridge/intel/gm45/Makefile.inc
parente119d86ca87937d45e67d00da722c28ac7ceaa9e (diff)
downloadcoreboot-fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886.tar.xz
northbridge/intel: Rename ram_calc.c to memmap.c
Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/gm45/Makefile.inc')
-rw-r--r--src/northbridge/intel/gm45/Makefile.inc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index b59a7c3cd2..0ab1c94a27 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -25,18 +25,18 @@ romstage-y += pcie.c
romstage-y += thermal.c
romstage-y += igd.c
romstage-y += pm.c
-romstage-y += ram_calc.c
+romstage-y += memmap.c
romstage-y += iommu.c
romstage-y += romstage.c
ramstage-y += acpi.c
-ramstage-y += ram_calc.c
+ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
smm-y += ../../../cpu/x86/lapic/apic_timer.c
-postcar-y += ram_calc.c
+postcar-y += memmap.c
endif