intel/gm45: new northbridge

The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
different that it requires separate code, and we have no boards to
test that.

Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

4 files changed, 701 insertions, 0 deletions

diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
new file mode 100644
index 0000000000..fac194b47a
--- /dev/null
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "hostbridge.asl"
+#include "../gm45.h"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 1)
+
+	// This does not seem to work correctly yet - set values statically for
+	// now.
+
+	//Name (PDRS, ResourceTemplate() {
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
+	//	Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
+	//})
+
+	Name (PDRS, ResourceTemplate() {
+		Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
+		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
+		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+	})
+
+	// Current Resource Settings
+	Method (_CRS, 0, Serialized)
+	{
+		//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
+		//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
+
+		//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
+
+		//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
+
+		//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
+
+		//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
+
+		//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
+		//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
+
+		Return(PDRS)
+	}
+}
+
+// PCIe graphics port 0:1.0
+#include "peg.asl"
+
+// Integrated graphics 0:2.0
+#include "igd.asl"
+
+Scope (\)
+{
+	// backlight control, display switching, lid
+	#include "acpi/video.asl"
+}
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
new file mode 100644
index 0000000000..3d70e54821
--- /dev/null
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/ioapic.h>
+
+Name(_HID,EISAID("PNP0A08"))	// PCIe
+Name(_CID,EISAID("PNP0A03"))	// PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Device (MCHC)
+{
+	Name(_ADR, 0x00000000)	// 0:0.0
+
+	OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
+	Field (MCHP, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x40),	// EPBAR
+		EPEN,	 1,	// Enable
+		,	11,	//
+		EPBR,	24,	// EPBAR
+
+		Offset (0x48),	// MCHBAR
+		MHEN,	 1,	// Enable
+		,	13,	//
+		MHBR,	22,	// MCHBAR
+
+		Offset (0x60),	// PCIe BAR
+		PXEN,	 1,	// Enable
+		PXSZ,	 2,	// BAR size
+		,	23,	//
+		PXBR,	10,	// PCIe BAR
+
+		Offset (0x68),	// DMIBAR
+		DMEN,	 1,	// Enable
+		,	11,	//
+		DMBR,	24,	// DMIBAR
+
+		// ...
+
+		Offset (0x90),	// PAM0
+		,	 4,
+		PM0H,	 2,
+		,	 2,
+		Offset (0x91),	// PAM1
+		PM1L,	 2,
+		,	 2,
+		PM1H,	 2,
+		,	 2,
+		Offset (0x92),	// PAM2
+		PM2L,	 2,
+		,	 2,
+		PM2H,	 2,
+		,	 2,
+		Offset (0x93),	// PAM3
+		PM3L,	 2,
+		,	 2,
+		PM3H,	 2,
+		,	 2,
+		Offset (0x94),	// PAM4
+		PM4L,	 2,
+		,	 2,
+		PM4H,	 2,
+		,	 2,
+		Offset (0x95),	// PAM5
+		PM5L,	 2,
+		,	 2,
+		PM5H,	 2,
+		,	 2,
+		Offset (0x96),	// PAM6
+		PM6L,	 2,
+		,	 2,
+		PM6H,	 2,
+		,	 2,
+
+		Offset (0xa0),	// Top of Used Memory
+		TOM,	 8,
+
+		Offset (0xb0),	// Top of Low Used Memory
+		,	 4,
+		TLUD,	12,
+	}
+
+}
+
+
+// Current Resource Settings
+
+Method (_CRS, 0, Serialized)
+{
+	Name (MCRS, ResourceTemplate()
+	{
+		// Bus Numbers
+		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+		// IO Region 0
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+		// PCI Config Space
+		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		// IO Region 1
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+		// VGA memory (0xa0000-0xbffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000,,, ASEG)
+
+		// OPROM reserved (0xc0000-0xc3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000,,, OPR0)
+
+		// OPROM reserved (0xc4000-0xc7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000,,, OPR1)
+
+		// OPROM reserved (0xc8000-0xcbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000,,, OPR2)
+
+		// OPROM reserved (0xcc000-0xcffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000,,, OPR3)
+
+		// OPROM reserved (0xd0000-0xd3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000,,, OPR4)
+
+		// OPROM reserved (0xd4000-0xd7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000,,, OPR5)
+
+		// OPROM reserved (0xd8000-0xdbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000,,, OPR6)
+
+		// OPROM reserved (0xdc000-0xdffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000,,, OPR7)
+
+		// BIOS Extension (0xe0000-0xe3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000,,, ESG0)
+
+		// BIOS Extension (0xe4000-0xe7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000,,, ESG1)
+
+		// BIOS Extension (0xe8000-0xebfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000,,, ESG2)
+
+		// BIOS Extension (0xec000-0xeffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000,,, ESG3)
+
+		// System BIOS (0xf0000-0xfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000,,, FSEG)
+
+		// PCI Memory Region (Top of memory-0xfebfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
+				IO_APIC_ADDR,,, PM01)
+
+		// TPM Area (0xfed40000-0xfed44fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+				0x00005000,,, TPMR)
+	})
+
+	// Find PCI resource area in MCRS
+	CreateDwordField(MCRS, PM01._MIN, PMIN)
+	CreateDwordField(MCRS, PM01._MAX, PMAX)
+	CreateDwordField(MCRS, PM01._LEN, PLEN)
+
+	// Fix up PCI memory region:
+	// Enter actual TOLUD. The TOLUD register contains bits 20-31 of
+	// the top of memory address.
+	ShiftLeft (^MCHC.TLUD, 20, PMIN)
+	Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+	Return (MCRS)
+}
+
+/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
+#include "acpi/gm45_pci_irqs.asl"
+
+
diff --git a/src/northbridge/intel/gm45/acpi/igd.asl b/src/northbridge/intel/gm45/acpi/igd.asl
new file mode 100644
index 0000000000..ba01d230b6
--- /dev/null
+++ b/src/northbridge/intel/gm45/acpi/igd.asl
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+
+	/* Display Output Switching */
+	Method (_DOS, 1)
+	{
+		/* Windows 2000 and Windows XP call _DOS to enable/disable
+		 * Display Output Switching during init and while a switch
+		 * is already active
+		 */
+		Store (And(Arg0, 7), DSEN)
+	}
+
+	/* We try to support as many GM45 systems as possible,
+	 * so keep the number of DIDs flexible.
+	 */
+	Method (_DOD, 0)
+	{
+		If (LEqual(NDID, 1)) {
+			Name(DOD1, Package() {
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD1, 0))
+			Return(DOD1)
+		}
+
+		If (LEqual(NDID, 2)) {
+			Name(DOD2, Package() {
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD2, 0))
+			Store (Or(0x00010000, DID2), Index(DOD2, 1))
+			Return(DOD2)
+		}
+
+		If (LEqual(NDID, 3)) {
+			Name(DOD3, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD3, 0))
+			Store (Or(0x00010000, DID2), Index(DOD3, 1))
+			Store (Or(0x00010000, DID3), Index(DOD3, 2))
+			Return(DOD3)
+		}
+
+		If (LEqual(NDID, 4)) {
+			Name(DOD4, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD4, 0))
+			Store (Or(0x00010000, DID2), Index(DOD4, 1))
+			Store (Or(0x00010000, DID3), Index(DOD4, 2))
+			Store (Or(0x00010000, DID4), Index(DOD4, 3))
+			Return(DOD4)
+		}
+
+		If (LGreater(NDID, 4)) {
+			Name(DOD5, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD5, 0))
+			Store (Or(0x00010000, DID2), Index(DOD5, 1))
+			Store (Or(0x00010000, DID3), Index(DOD5, 2))
+			Store (Or(0x00010000, DID4), Index(DOD5, 3))
+			Store (Or(0x00010000, DID5), Index(DOD5, 4))
+			Return(DOD5)
+		}
+
+		/* Some error happened, but we have to return something */
+		Return (Package() {0x00000400})
+	}
+
+	Device(DD01)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID1, 0)) {
+				Return (1)
+			} Else {
+				Return (And(0xffff, DID1))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 1)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 1)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+	Device(DD02)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID2, 0)) {
+				Return (2)
+			} Else {
+				Return (And(0xffff, DID2))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 2)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 2)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD03)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID3, 0)) {
+				Return (3)
+			} Else {
+				Return (And(0xffff, DID3))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 4)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD04)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID4, 0)) {
+				Return (4)
+			} Else {
+				Return (And(0xffff, DID4))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 8)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD05)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID5, 0)) {
+				Return (5)
+			} Else {
+				Return (And(0xffff, DID5))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 16)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+}
+
diff --git a/src/northbridge/intel/gm45/acpi/peg.asl b/src/northbridge/intel/gm45/acpi/peg.asl
new file mode 100644
index 0000000000..bc7f8f7578
--- /dev/null
+++ b/src/northbridge/intel/gm45/acpi/peg.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (PEGP)
+{
+	Name (_ADR, 0x00010000)
+
+	// PCI Interrupt Routing.
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 16 },
+				Package() { 0x0000ffff, 1, 0, 17 },
+				Package() { 0x0000ffff, 2, 0, 18 },
+				Package() { 0x0000ffff, 3, 0, 19 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+			})
+		}
+
+	}
+}
+