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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-11-24 13:23:05 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-11-28 19:24:12 +0100 |
| commit | 12bed2608f2f98fd41f6dac9c918123f51e830d4 (patch) | |
| tree | 16cf601292493934479de819916e1482bf8c5910 /src/northbridge/intel/gm45/chip.h | |
| parent | ea08ad7188eee27ad03c75ddc679a68737b4b74a (diff) | |
| download | coreboot-12bed2608f2f98fd41f6dac9c918123f51e830d4.tar.xz | |
nb/gm45/gma.c: Compute BLC_PWM_CTL value from PWM frequency
This allows to set the backlight PWM frequency and the
duty cycle in the devicetree instead of using a plain BLC_PWM_CTL
value.
Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17597
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/gm45/chip.h')
| -rw-r--r-- | src/northbridge/intel/gm45/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 836d6bb737..a281ee96d9 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,6 +26,8 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; + u16 pwm_freq; + u8 duty_cycle; /* * Maximum PCI mmio size in MiB. |