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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-29 14:31:32 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2017-05-03 16:19:03 +0200 |
commit | 20cb85fa985206fe1d51f87d4fcb9c95e5b44f7a (patch) | |
tree | ffd861017cd549c4f1aefd8a82b920620e7cf367 /src/northbridge/intel/gm45/chip.h | |
parent | dbe81612adba70d02831ffae57dd406fa08785b8 (diff) | |
download | coreboot-20cb85fa985206fe1d51f87d4fcb9c95e5b44f7a.tar.xz |
nb/intel/gm45: Set display backlight according to EDID string
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/gm45/chip.h')
-rw-r--r-- | src/northbridge/intel/gm45/chip.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index a281ee96d9..150dd9b33d 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -26,7 +26,7 @@ struct northbridge_intel_gm45_config { u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ struct i915_gpu_controller_info gfx; - u16 pwm_freq; + u16 default_pwm_freq; u8 duty_cycle; /* |