diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-01 11:21:53 +0300 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:19:58 +0200 |
commit | 35a7249183d2e791eb00b41332e6277c504cdd49 (patch) | |
tree | ca73ef3d75e19dafad5fdea0cce1abcfdcd7d234 /src/northbridge/intel/gm45/early_init.c | |
parent | 25dd2479c1890d45935d7dbfc14599385e1893dd (diff) | |
download | coreboot-35a7249183d2e791eb00b41332e6277c504cdd49.tar.xz |
intel/gm45: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO for all boards
with gm45 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3600
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/gm45/early_init.c')
-rw-r--r-- | src/northbridge/intel/gm45/early_init.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 052c517781..ed5bf99210 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -25,11 +25,6 @@ void gm45_early_init(void) { const device_t d0f0 = PCI_DEV(0, 0, 0); - /* Setup PCIEXBAR. */ - pci_io_write_config32(d0f0, D0F0_PCIEXBAR_LO, - /* 64MB, enable */ - DEFAULT_PCIEXBAR | (2 << 1) | 1); - /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); |