diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-24 23:25:13 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-28 06:49:19 +0000 |
commit | 8b76605a4af9b45894c39cd7b9c480bd96f523cd (patch) | |
tree | 4d24a5aa80b7e6e1b19ef62868fc442aa1a8c128 /src/northbridge/intel/gm45/northbridge.c | |
parent | a050817ce57ef960bf2bec3a18f23b59039dd184 (diff) | |
download | coreboot-8b76605a4af9b45894c39cd7b9c480bd96f523cd.tar.xz |
nb/intel/gm45: Allocate a 8M TSEG region
Tested on Thinkpad X200.
Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/northbridge.c')
-rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8215979267..4927e53765 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -119,16 +119,21 @@ static void mch_domain_read_resources(device_t dev) /* Graphics memory */ const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); - printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10); tomk -= gms_sizek; /* GTT Graphics Stolen Memory Size (GGMS) */ const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); - printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10); tomk -= gsm_sizek; uma_sizek = gms_sizek + gsm_sizek; } + const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); + const u32 tseg_sizek = decode_tseg_size(esmramc); + printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10); + tomk -= tseg_sizek; + uma_sizek += tseg_sizek; printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |