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author | Nico Huber <nico.h@gmx.de> | 2017-04-15 15:57:28 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-04-19 16:25:11 +0200 |
commit | 0624f9211892d1bd81f2967e8a715a031ad50b11 (patch) | |
tree | f7baf31d9b5ec47202869e007927f322ca7b8fb4 /src/northbridge/intel/gm45/raminit.c | |
parent | 35e6eb1cef070987ef69fb04e61a2ce900c32204 (diff) | |
download | coreboot-0624f9211892d1bd81f2967e8a715a031ad50b11.tar.xz |
nb/intel/gm45: Hide some output behind DEBUG_RAM_SETUP
Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten
some messages. This saves some KiB to make CBMEM console more
usable in romstage.
Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/gm45/raminit.c')
-rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 0435cddc24..30e9297a06 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1593,7 +1593,7 @@ static void jedec_init(const timings_t *const timings, /* We won't do this in dual-interleaved mode, so don't care about the offset. */ const u32 rankaddr = raminit_get_rank_addr(ch, r); - printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr); + printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); read32((u32 *)(rankaddr | WL)); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3); |