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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-24 23:25:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-28 06:49:19 +0000 |
| commit | 8b76605a4af9b45894c39cd7b9c480bd96f523cd (patch) | |
| tree | 4d24a5aa80b7e6e1b19ef62868fc442aa1a8c128 /src/northbridge/intel/gm45/raminit.c | |
| parent | a050817ce57ef960bf2bec3a18f23b59039dd184 (diff) | |
| download | coreboot-8b76605a4af9b45894c39cd7b9c480bd96f523cd.tar.xz | |
nb/intel/gm45: Allocate a 8M TSEG region
Tested on Thinkpad X200.
Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/raminit.c')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index a44e3975be..af5faf0caf 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1242,6 +1242,12 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode uma_sizem = (gms_sizek + gsm_sizek) >> 10; } + /* TSEG 8M */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + reg8 &= ~0x7; + reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */ + pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); + uma_sizem += 8; } const unsigned int mmio_size = get_mmio_size(); |