diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-27 13:52:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-04-10 16:04:20 +0000 |
| commit | 3f1f8ef931aa92c72006dd363d178336911e224c (patch) | |
| tree | 873d802eb3bfbae15eeb58da8b87de88b062c122 /src/northbridge/intel/gm45/raminit_receive_enable_calibration.c | |
| parent | 677ac698680f31a83086245f3b741dcb79da6fc4 (diff) | |
| download | coreboot-3f1f8ef931aa92c72006dd363d178336911e224c.tar.xz | |
nb/intel/gm45: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51880
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45/raminit_receive_enable_calibration.c')
| -rw-r--r-- | src/northbridge/intel/gm45/raminit_receive_enable_calibration.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 6d95b3401b..0b1c789ef9 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -110,29 +110,28 @@ static void program_timing(int channel, int group, /* C value is per channel. */ unsigned int mchbar = CxDRT3_MCHBAR(channel); - MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | - CxDRT3_C(timing->c); + mchbar_clrsetbits32(mchbar, CxDRT3_C_MASK, CxDRT3_C(timing->c)); /* All other per group. */ mchbar = CxRECy_MCHBAR(channel, group); - u32 reg = MCHBAR32(mchbar); + u32 reg = mchbar_read32(mchbar); reg &= ~CxRECy_TIMING_MASK; reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | CxRECy_PH(timing->ph) | CxRECy_PM(timing->pre); - MCHBAR32(mchbar) = reg; + mchbar_write32(mchbar, reg); } static int read_dqs_level(const int channel, const int lane) { unsigned int mchbar = 0x14f0 + (channel * 0x0100); - MCHBAR32(mchbar) &= ~(1 << 9); - MCHBAR32(mchbar) |= (1 << 9); + mchbar_clrbits32(mchbar, 1 << 9); + mchbar_setbits32(mchbar, 1 << 9); /* Read from this channel. */ read32((u32 *)raminit_get_rank_addr(channel, 0)); mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); - return MCHBAR32(mchbar) & (1 << 30); + return mchbar_read32(mchbar) & (1 << 30); } static void find_dqs_low(const int channel, const int group, @@ -272,22 +271,22 @@ void raminit_receive_enable_calibration(const timings_t *const timings, unsigned int group; for (group = 0; group < 4; ++group) { const unsigned int mchbar = CxRECy_MCHBAR(ch, group); - u32 reg = MCHBAR32(mchbar); + u32 reg = mchbar_read32(mchbar); reg &= ~((3 << 16) | (1 << 8) | 3); reg |= (map[group][0] - group); reg |= (map[group][1] - group - 1) << 16; - MCHBAR32(mchbar) = reg; + mchbar_write32(mchbar, reg); } } - MCHBAR32(0x12a4) |= 1 << 31; - MCHBAR32(0x13a4) |= 1 << 31; - MCHBAR32(0x14f0) = (MCHBAR32(0x14f0) & ~(3 << 9)) | (1 << 9); - MCHBAR32(0x15f0) = (MCHBAR32(0x15f0) & ~(3 << 9)) | (1 << 9); + mchbar_setbits32(0x12a4, 1 << 31); + mchbar_setbits32(0x13a4, 1 << 31); + mchbar_clrsetbits32(0x14f0, 3 << 9, 1 << 9); + mchbar_clrsetbits32(0x15f0, 3 << 9, 1 << 9); receive_enable_calibration(timings, dimms); - MCHBAR32(0x12a4) &= ~(1 << 31); - MCHBAR32(0x13a4) &= ~(1 << 31); + mchbar_clrbits32(0x12a4, 1 << 31); + mchbar_clrbits32(0x13a4, 1 << 31); raminit_reset_readwrite_pointers(); } |