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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-02 06:11:28 +0300 |
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committer | Martin Roth <martinroth@google.com> | 2019-08-03 17:36:01 +0000 |
commit | aba8fb115802df289007ae9df3269d65cfd008c5 (patch) | |
tree | bcc7d7fd9a8b32f408b1446d158e7520fcc0abce /src/northbridge/intel/gm45/stage_cache.c | |
parent | 26a682c9441b4f7312ff9f69d22029841aa245bd (diff) | |
download | coreboot-aba8fb115802df289007ae9df3269d65cfd008c5.tar.xz |
intel/i945,gm45,pineview,x4x: Move stage cache support function
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.
Change-Id: Ic32adcc62c7ee21bf38e2e4e5ece00524871b091
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/gm45/stage_cache.c')
-rw-r--r-- | src/northbridge/intel/gm45/stage_cache.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/northbridge/intel/gm45/stage_cache.c b/src/northbridge/intel/gm45/stage_cache.c deleted file mode 100644 index 47f08c1397..0000000000 --- a/src/northbridge/intel/gm45/stage_cache.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)(northbridge_get_tseg_base() - + CONFIG_SMM_RESERVED_SIZE); -} |