diff options
author | Angel Pons <th3fanbus@gmail.com> | 2021-03-27 13:52:43 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2021-04-10 16:04:20 +0000 |
commit | 3f1f8ef931aa92c72006dd363d178336911e224c (patch) | |
tree | 873d802eb3bfbae15eeb58da8b87de88b062c122 /src/northbridge/intel/gm45 | |
parent | 677ac698680f31a83086245f3b741dcb79da6fc4 (diff) | |
download | coreboot-3f1f8ef931aa92c72006dd363d178336911e224c.tar.xz |
nb/intel/gm45: Use new fixed BAR accessors
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51880
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r-- | src/northbridge/intel/gm45/early_reset.c | 31 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/gma.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/igd.c | 16 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/iommu.c | 16 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 141 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/pm.c | 231 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 491 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/raminit_rcomp_calibration.c | 36 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/raminit_read_write_training.c | 34 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/raminit_receive_enable_calibration.c | 29 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/romstage.c | 6 | ||||
-rw-r--r-- | src/northbridge/intel/gm45/thermal.c | 174 |
12 files changed, 598 insertions, 609 deletions
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 17838809fa..15591c1c0a 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -12,8 +12,7 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Reset DRAM power-up settings in CLKCFG (they are not affected by system reset but may disrupt raminit). */ - MCHBAR32(CLKCFG_MCHBAR) = - (MCHBAR32(CLKCFG_MCHBAR) & ~(3 << 21)) | (1 << 3); + mchbar_clrsetbits32(CLKCFG_MCHBAR, 3 << 21, 1 << 3); /*\ Next settings are the real purpose of this function: If these steps are not performed, reset results in power off. \*/ @@ -21,33 +20,31 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Initialize some DRAM settings to 1 populated rank of 128MB. */ FOR_EACH_CHANNEL(ch) { /* Configure DRAM control mode. */ - MCHBAR32(CxDRC0_MCHBAR(ch)) = - (MCHBAR32(CxDRC0_MCHBAR(ch)) & ~CxDRC0_RANKEN_MASK) | - (ch ? 0 : CxDRC0_RANKEN(0)); - MCHBAR32(CxDRC1_MCHBAR(ch)) = - (MCHBAR32(CxDRC1_MCHBAR(ch)) | CxDRC1_NOTPOP_MASK) & - ~(ch ? 0 : CxDRC1_NOTPOP(0)); - MCHBAR32(CxDRC2_MCHBAR(ch)) = - (MCHBAR32(CxDRC2_MCHBAR(ch)) | CxDRC2_NOTPOP_MASK) & - ~(ch ? 0 : CxDRC2_NOTPOP(0)); + mchbar_clrsetbits32(CxDRC0_MCHBAR(ch), CxDRC0_RANKEN_MASK, + (ch ? 0 : CxDRC0_RANKEN(0))); + mchbar_write32(CxDRC1_MCHBAR(ch), + (mchbar_read32(CxDRC1_MCHBAR(ch)) | CxDRC1_NOTPOP_MASK) & + ~(ch ? 0 : CxDRC1_NOTPOP(0))); + mchbar_write32(CxDRC2_MCHBAR(ch), + (mchbar_read32(CxDRC2_MCHBAR(ch)) | CxDRC2_NOTPOP_MASK) & + ~(ch ? 0 : CxDRC2_NOTPOP(0))); /*if (timings && (timings->mem_clock == MEM_CLOCK_1067MT)) - MCHBAR32(CxDRC2_MCHBAR(ch)) |= CxDRC2_CLK1067MT;*/ + mchbar_setbits32(CxDRC2_MCHBAR(ch), CxDRC2_CLK1067MT);*/ /* Program rank boundaries (CxDRBy). */ for (r = 0; r < RANKS_PER_CHANNEL; r += 2) - MCHBAR32(CxDRBy_MCHBAR(ch, r)) = - CxDRBy_BOUND_MB(r, 128) | - CxDRBy_BOUND_MB(r+1, 128); + mchbar_write32(CxDRBy_MCHBAR(ch, r), + CxDRBy_BOUND_MB(r, 128) | CxDRBy_BOUND_MB(r + 1, 128)); } /* Set DCC mode to no operation and do magic 0xf0 thing. */ - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; + mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP); pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2)); /* Normally, we would set this after successful raminit. */ - MCHBAR32(DCC_MCHBAR) |= (1 << 19); + mchbar_setbits32(DCC_MCHBAR, 1 << 19); system_reset(); } diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index c771ea2deb..178149d119 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -33,7 +33,7 @@ static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK; - switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { + switch (mchbar_read8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: case VCO_4000: case VCO_5333: diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 102af1c4c3..f4a0e0c682 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -22,8 +22,8 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) printk(BIOS_DEBUG, "Enabling IGD.\n"); /* HSync/VSync */ - MCHBAR8(0xbd0 + 3) = 0x5a; - MCHBAR8(0xbd0 + 4) = 0x5a; + mchbar_write8(0xbd0 + 3, 0x5a); + mchbar_write8(0xbd0 + 4, 0x5a); static const u16 display_clock_from_f0_and_vco[][4] = { /* VCO 2666 VCO 3200 VCO 4000 VCO 5333 */ @@ -58,7 +58,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) /* Disable PEG finally. */ printk(BIOS_DEBUG, "Finally disabling " "PEG in favor of IGD.\n"); - MCHBAR8(0xc14) |= (1 << 5) | (1 << 0); + mchbar_setbits8(0xc14, 1 << 5 | 1 << 0); pci_or_config32(peg_dev, 0x200, 1 << 18); @@ -70,7 +70,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) ; pci_write_config32(mch_dev, D0F0_DEVEN, deven & ~2); - MCHBAR8(0xc14) &= ~((1 << 5) | (1 << 0)); + mchbar_clrbits8(0xc14, 1 << 5 | 1 << 0); } } } @@ -84,12 +84,12 @@ static void disable_igd(const sysinfo_t *const sysinfo) /* Disable Graphics Stolen Memory. */ pci_update_config16(mch_dev, D0F0_GGC, 0xff0f, 0x0002); - MCHBAR8(0xf10) |= (1 << 0); + mchbar_setbits8(0xf10, 1 << 0); if (!(pci_read_config8(mch_dev, D0F0_CAPID0 + 4) & (1 << (33 - 32)))) { - MCHBAR16(0x1190) |= (1 << 14); - MCHBAR16(0x119e) = (MCHBAR16(0x119e) & ~(7 << 13)) | (4 << 13); - MCHBAR16(0x119e) |= (1 << 12); + mchbar_setbits16(0x1190, 1 << 14); + mchbar_clrsetbits16(0x119e, 7 << 13, 4 << 13); + mchbar_setbits16(0x119e, 1 << 12); } /* Hide IGD. */ diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 09df12d18a..a961481188 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -14,21 +14,21 @@ void init_iommu() int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); - MCHBAR32(0x28) = IOMMU_BASE1 | 1; /* HDA @ 0:1b.0 */ + mchbar_write32(0x28, IOMMU_BASE1 | 1); /* HDA @ 0:1b.0 */ if (stepping != STEPPING_B2) { /* The official workaround is to run SMM every 64ms. The only winning move is not to play. */ - MCHBAR32(0x18) = IOMMU_BASE2 | 1; /* IGD @ 0:2.0-1 */ + mchbar_write32(0x18, IOMMU_BASE2 | 1); /* IGD @ 0:2.0-1 */ } else { /* write-once, so lock it down */ - MCHBAR32(0x18) = 0; /* disable IOMMU for IGD @ 0:2.0-1 */ + mchbar_write32(0x18, 0); /* disable IOMMU for IGD @ 0:2.0-1 */ } if (me_active) { - MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ + mchbar_write32(0x10, IOMMU_BASE3 | 1); /* ME @ 0:3.0-3 */ } else { - MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ + mchbar_write32(0x10, 0); /* disable IOMMU for ME */ } - MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ + mchbar_write32(0x20, IOMMU_BASE4 | 1); /* all other DMA sources */ /* clear GTT */ u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); @@ -48,7 +48,7 @@ void init_iommu() } if (stepping == STEPPING_B3) { - MCHBAR8(0xffc) |= 1 << 4; + mchbar_setbits8(0xffc, 1 << 4); const pci_devfn_t peg = PCI_DEV(0, 1, 0); /* FIXME: proper test? */ @@ -57,5 +57,5 @@ void init_iommu() } /* final */ - MCHBAR8(0x94) |= 1 << 3; + mchbar_setbits8(0x94, 1 << 3); } diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 4ccd2d61ff..295bf5b0c9 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -11,34 +11,34 @@ static void init_egress(void) { /* VC0: TC0 only */ - EPBAR8(EPVC0RCTL) &= 1; - EPBAR8(EPPVCCAP1) = (EPBAR8(EPPVCCAP1) & ~7) | 1; + epbar_clrbits8(EPVC0RCTL, ~1); + epbar_clrsetbits8(EPPVCCAP1, 7, 1); /* VC1: isoch */ - EPBAR32(EPVC1MTS) = 0x0a0a0a0a; - EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~(127 << 16)) | (0x0a << 16); + epbar_write32(EPVC1MTS, 0x0a0a0a0a); + epbar_clrsetbits32(EPVC1RCAP, 127 << 16, 0x0a << 16); /* VC1: ID1, TC7 */ - EPBAR32(EPVC1RCTL) = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24); - EPBAR8(EPVC1RCTL) = (EPBAR8(EPVC1RCTL) & 1) | (1 << 7); + epbar_clrsetbits32(EPVC1RCTL, 7 << 24, 1 << 24); + epbar_clrsetbits8(EPVC1RCTL, ~1, 1 << 7); /* VC1 ARB table: setup and enable */ - EPBAR32(EP_PORTARB(0)) = 0x55555555; - EPBAR32(EP_PORTARB(1)) = 0x55555555; - EPBAR32(EP_PORTARB(2)) = 0x55555555; - EPBAR32(EP_PORTARB(3)) = 0x55555555; - EPBAR32(EP_PORTARB(4)) = 0x55555555; - EPBAR32(EP_PORTARB(5)) = 0x55555555; - EPBAR32(EP_PORTARB(6)) = 0x55555555; - EPBAR32(EP_PORTARB(7)) = 0x00005555; - EPBAR32(EPVC1RCTL) |= 1 << 16; - - while ((EPBAR8(EPVC1RSTS) & 1) != 0); + epbar_write32(EP_PORTARB(0), 0x55555555); + epbar_write32(EP_PORTARB(1), 0x55555555); + epbar_write32(EP_PORTARB(2), 0x55555555); + epbar_write32(EP_PORTARB(3), 0x55555555); + epbar_write32(EP_PORTARB(4), 0x55555555); + epbar_write32(EP_PORTARB(5), 0x55555555); + epbar_write32(EP_PORTARB(6), 0x55555555); + epbar_write32(EP_PORTARB(7), 0x00005555); + epbar_setbits32(EPVC1RCTL, 1 << 16); + + while ((epbar_read8(EPVC1RSTS) & 1) != 0); /* VC1: enable */ - EPBAR32(EPVC1RCTL) |= 1 << 31; + epbar_setbits32(EPVC1RCTL, 1 << 31); - while ((EPBAR8(EPVC1RSTS) & 2) != 0); + while ((epbar_read8(EPVC1RSTS) & 2) != 0); } /* MCH side */ @@ -46,47 +46,47 @@ static void init_egress(void) static void init_dmi(int b2step) { /* VC0: TC0 only */ - DMIBAR8(DMIVC0RCTL) &= 1; - DMIBAR8(DMIPVCCAP1) = (DMIBAR8(DMIPVCCAP1) & ~7) | 1; + dmibar_clrbits8(DMIVC0RCTL, ~1); + dmibar_clrsetbits8(DMIPVCCAP1, 7, 1); /* VC1: ID1, TC7 */ - DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24); - DMIBAR8(DMIVC1RCTL) = (DMIBAR8(DMIVC1RCTL) & 1) | (1 << 7); + dmibar_clrsetbits32(DMIVC1RCTL, 7 << 24, 1 << 24); + dmibar_clrsetbits8(DMIVC1RCTL, ~1, 1 << 7); /* VC1: enable */ - DMIBAR32(DMIVC1RCTL) |= 1 << 31; + dmibar_setbits32(DMIVC1RCTL, 1 << 31); - while ((DMIBAR8(DMIVC1RSTS) & VC1NP) != 0); + while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0); /* additional configuration. */ - DMIBAR32(0x200) |= 3 << 13; - DMIBAR32(0x200) &= ~(1 << 21); - DMIBAR32(0x200) = (DMIBAR32(0x200) & ~(3 << 26)) | (2 << 26); - DMIBAR32(0x2c) = 0x86000040; - DMIBAR32(0xfc) |= 1 << 0; - DMIBAR32(0xfc) |= 1 << 1; - DMIBAR32(0xfc) |= 1 << 4; + dmibar_setbits32(0x200, 3 << 13); + dmibar_clrbits32(0x200, 1 << 21); + dmibar_clrsetbits32(0x200, 3 << 26, 2 << 26); + dmibar_write32(0x2c, 0x86000040); + dmibar_setbits32(0xfc, 1 << 0); + dmibar_setbits32(0xfc, 1 << 1); + dmibar_setbits32(0xfc, 1 << 4); if (!b2step) { - DMIBAR32(0xfc) |= 1 << 11; + dmibar_setbits32(0xfc, 1 << 11); } else { - DMIBAR32(0xfc) &= ~(1 << 11); + dmibar_clrbits32(0xfc, 1 << 11); } - DMIBAR32(0x204) &= ~(3 << 10); - DMIBAR32(0xf4) &= ~(1 << 4); - DMIBAR32(0xf0) |= 3 << 24; - DMIBAR32(0xf04) = 0x07050880; - DMIBAR32(0xf44) = 0x07050880; - DMIBAR32(0xf84) = 0x07050880; - DMIBAR32(0xfc4) = 0x07050880; + dmibar_clrbits32(0x204, 3 << 10); + dmibar_clrbits32(0xf4, 1 << 4); + dmibar_setbits32(0xf0, 3 << 24); + dmibar_write32(0xf04, 0x07050880); + dmibar_write32(0xf44, 0x07050880); + dmibar_write32(0xf84, 0x07050880); + dmibar_write32(0xfc4, 0x07050880); /* lock down write-once registers DMIBAR32(0x84) will be set in setup_aspm(). */ - DMIBAR32(0x308) = DMIBAR32(0x308); - DMIBAR32(0x314) = DMIBAR32(0x314); - DMIBAR32(0x324) = DMIBAR32(0x324); - DMIBAR32(0x328) = DMIBAR32(0x328); - DMIBAR32(0x334) = DMIBAR32(0x334); - DMIBAR32(0x338) = DMIBAR32(0x338); + dmibar_setbits32(0x308, 0); + dmibar_setbits32(0x314, 0); + dmibar_setbits32(0x324, 0); + dmibar_setbits32(0x328, 0); + dmibar_setbits32(0x334, 0); + dmibar_setbits32(0x338, 0); } static void init_pcie(const int peg_enabled, @@ -185,16 +185,14 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) tmp32 &= ~(1 << 13); pci_write_config32(pciex, 0x0fc, tmp32); } - DMIBAR8 (0x0e1c) |= (1 << 0); - DMIBAR16(0x0f00) |= (3 << 8); - DMIBAR16(0x0f00) |= (7 << 3); - DMIBAR32(0x0f14) &= ~(1 << 17); - DMIBAR16(0x0e1c) &= ~(1 << 8); + dmibar_setbits8(0x0e1c, 1 << 0); + dmibar_setbits16(0x0f00, 3 << 8); + dmibar_setbits16(0x0f00, 7 << 3); + dmibar_clrbits32(0x0f14, 1 << 17); + dmibar_clrbits16(0x0e1c, 1 << 8); if (stepping >= STEPPING_B0) { - DMIBAR32(0x0e28 + 4) = (DMIBAR32(0x0e28 + 4) & - ~(0xf << (52 - 32))) | - (0xd << (52 - 32)); - DMIBAR32(0x0e2c) = 0x88d07333; + dmibar_clrsetbits32(0x0e28 + 4, 0xf << (52 - 32), 0xd << (52 - 32)); + dmibar_write32(0x0e2c, 0x88d07333); } if (peg_enabled) { pci_and_config32(pciex, 0xa08, ~(1 << 15)); @@ -224,13 +222,13 @@ static void setup_aspm(const stepping_t stepping, const int peg_enabled) the endpoint (ICH), but ICH doesn't give any limits. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) - DMIBAR8(DMILCTL) |= (3 << 0); // enable ASPM L0s, L1 (write-once) + dmibar_setbits8(DMILCTL, 3 << 0); // enable ASPM L0s, L1 (write-once) else - DMIBAR8(DMILCTL) |= (1 << 0); // enable ASPM L0s (write-once) + dmibar_setbits8(DMILCTL, 1 << 0); // enable ASPM L0s (write-once) /* timing */ - DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~(63 << 12)) | (2 << 12) | (2 << 15); - DMIBAR8(0x208 + 3) = 0; - DMIBAR32(0x208) &= ~(3 << 20); + dmibar_clrsetbits32(DMILCAP, 63 << 12, 2 << 12 | 2 << 15); + dmibar_write8(0x208 + 3, 0); + dmibar_clrbits32(0x208, 3 << 20); /*\ Setup ASPM on PEG \*/ /* @@ -247,36 +245,35 @@ static void setup_rcrb(const int peg_enabled) /*\ RCRB setup: Egress Port \*/ /* Set component ID of MCH (1). */ - EPBAR8(EPESD + 2) = 1; + epbar_write8(EPESD + 2, 1); /* Link1: component ID 1, link valid. */ - EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; + epbar_clrsetbits32(EPLE1D, 0xffffff, 1 << 16 | 1 << 0); + epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE); if (peg_enabled) /* Link2: link_valid. */ - EPBAR8(EPLE2D) |= (1 << 0); /* link valid */ + epbar_setbits8(EPLE2D, 1 << 0); /* link valid */ /*\ RCRB setup: DMI Port \*/ /* Set component ID of MCH (1). */ - DMIBAR8(DMIESD + 2) = 1; + dmibar_write8(DMIESD + 2, 1); /* Link1: target port 0, component id 2 (ICH), link valid. */ - DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0); - DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; + dmibar_write32(DMILE1D, 0 << 24 | 2 << 16 | 1 << 0); + dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE); /* Link2: component ID 1 (MCH), link valid */ - DMIBAR32(DMILE2D) = - (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = CONFIG_FIXED_MCHBAR_MMIO_BASE; + dmibar_clrsetbits32(DMILE2D, 0xffffff, 1 << 16 | 1 << 0); + dmibar_write32(DMILE2A, CONFIG_FIXED_MCHBAR_MMIO_BASE); } void gm45_late_init(const stepping_t stepping) { const pci_devfn_t mch = PCI_DEV(0, 0, 0); const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; - const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1; + const int sdvo_enabled = mchbar_read16(0x40) >> 8 & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled); init_egress(); diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index 680435baca..f1b7abc89b 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -28,7 +28,7 @@ static void init_freq_scaling(const gmch_gfx_t sku, const int low_power_mode) { int i; - MCHBAR32(0x11cc) = (MCHBAR32(0x11cc) & ~(0x1f)) | 0x17; + mchbar_clrsetbits32(0x11cc, 0x1f, 0x17); switch (sku) { case GMCH_GM45: case GMCH_GE45: @@ -43,14 +43,14 @@ static void init_freq_scaling(const gmch_gfx_t sku, const int low_power_mode) static const u32 voltage_mask = (0x1f << 24) | (0x1f << 16) | (0x1f << 8) | 0x1f; - MCHBAR32(0x1120) = (MCHBAR32(0x1120) & ~voltage_mask) | 0x10111213; - MCHBAR32(0x1124) = (MCHBAR32(0x1124) & ~voltage_mask) | 0x14151617; - MCHBAR32(0x1128) = (MCHBAR32(0x1128) & ~voltage_mask) | 0x18191a1b; - MCHBAR32(0x112c) = (MCHBAR32(0x112c) & ~voltage_mask) | 0x1c1d1e1f; - MCHBAR32(0x1130) = (MCHBAR32(0x1130) & ~voltage_mask) | 0x00010203; - MCHBAR32(0x1134) = (MCHBAR32(0x1134) & ~voltage_mask) | 0x04050607; - MCHBAR32(0x1138) = (MCHBAR32(0x1138) & ~voltage_mask) | 0x08090a0b; - MCHBAR32(0x113c) = (MCHBAR32(0x113c) & ~voltage_mask) | 0x0c0d0e0f; + mchbar_clrsetbits32(0x1120, voltage_mask, 0x10111213); + mchbar_clrsetbits32(0x1124, voltage_mask, 0x14151617); + mchbar_clrsetbits32(0x1128, voltage_mask, 0x18191a1b); + mchbar_clrsetbits32(0x112c, voltage_mask, 0x1c1d1e1f); + mchbar_clrsetbits32(0x1130, voltage_mask, 0x00010203); + mchbar_clrsetbits32(0x1134, voltage_mask, 0x04050607); + mchbar_clrsetbits32(0x1138, voltage_mask, 0x08090a0b); + mchbar_clrsetbits32(0x113c, voltage_mask, 0x0c0d0e0f); /* Program frequencies. */ static const u32 frequencies_from_sku_vco[][4][8] = { @@ -82,43 +82,40 @@ static void init_freq_scaling(const gmch_gfx_t sku, const int low_power_mode) const int vco_index = raminit_read_vco_index(); const int reg_limit = low_power_mode ? 1 : 4; if (sku == GMCH_GM49) - MCHBAR8(0x1110+3) = 0x1b; + mchbar_write8(0x1110 + 3, 0x1b); else - MCHBAR8(0x1110+3) = 0x17; - MCHBAR8(0x1110+1) = 0x17; + mchbar_write8(0x1110 + 3, 0x17); + mchbar_write8(0x1110 + 1, 0x17); if (!low_power_mode) { - MCHBAR8(0x1114+3) = 0x17; - MCHBAR8(0x1114+1) = 0x17; - MCHBAR8(0x1118+3) = 0x17; - MCHBAR8(0x1118+1) = 0x17; - MCHBAR8(0x111c+3) = 0x17; - MCHBAR8(0x111c+1) = 0x17; + mchbar_write8(0x1114 + 3, 0x17); + mchbar_write8(0x1114 + 1, 0x17); + mchbar_write8(0x1118 + 3, 0x17); + mchbar_write8(0x1118 + 1, 0x17); + mchbar_write8(0x111c + 3, 0x17); + mchbar_write8(0x111c + 1, 0x17); } for (i = 0; i < reg_limit; ++i) { const int mchbar = 0x1110 + (i * 4); - MCHBAR8(mchbar + 2) = frequencies_from_sku_vco - [sku_index][vco_index][i * 2 + 0]; - MCHBAR8(mchbar + 0) = frequencies_from_sku_vco - [sku_index][vco_index][i * 2 + 1]; + mchbar_write8(mchbar + 2, frequencies_from_sku_vco + [sku_index][vco_index][i * 2 + 0]); + mchbar_write8(mchbar + 0, frequencies_from_sku_vco + [sku_index][vco_index][i * 2 + 1]); } if (low_power_mode) { - MCHBAR16(0x1190) = - (MCHBAR16(0x1190) & ~((7 << 8) | (7 << 4) | 7)) | - (1 << 8) | (1 << 4) | 1; + mchbar_clrsetbits16(0x1190, 7 << 8 | 7 << 4 | 7, 1 << 8 | 1 << 4 | 1); } else { - MCHBAR16(0x1190) = - (MCHBAR16(0x1190) & ~((7 << 8) | (7 << 4))) | 7; + mchbar_clrsetbits16(0x1190, 7 << 8 | 7 << 4, 7); if (sku == GMCH_GS45) /* performance mode */ - MCHBAR32(0x0ffc) &= ~(1 << 31); + mchbar_clrbits32(0x0ffc, 1 << 31); } - MCHBAR16(0x0fc0) |= (1 << 11); - MCHBAR16(0x11b8) = 0x333c; - MCHBAR16(0x11c0 + 2) = 0x0303; - MCHBAR32(0x11c4) = 0x0a030a03; - MCHBAR16(0x1100) = (MCHBAR16(0x1100) & ~(0x1f << 8)) | (3 << 8); - MCHBAR16(0x11b8 + 2) = 0x4000; + mchbar_setbits16(0x0fc0, 1 << 11); + mchbar_write16(0x11b8, 0x333c); + mchbar_write16(0x11c0 + 2, 0x0303); + mchbar_write32(0x11c4, 0x0a030a03); + mchbar_clrsetbits16(0x1100, 0x1f << 8, 3 << 8); + mchbar_write16(0x11b8 + 2, 0x4000); } void init_pm(const sysinfo_t *const sysinfo, int do_freq_scaling_cfg) @@ -127,138 +124,138 @@ void init_pm(const sysinfo_t *const sysinfo, int do_freq_scaling_cfg) const fsb_clock_t fsb = sysinfo->selected_timings.fsb_clock; const mem_clock_t memclk = sysinfo->selected_timings.mem_clock; - MCHBAR16(0xc14) = 0; - MCHBAR16(0xc20) = 0; - MCHBAR32(0xfc0) = 0x001f00fd; - MCHBAR32(0xfc0) |= 3 << 25; - MCHBAR32(0xfc0) |= 1 << 11; - MCHBAR8(0xfb0) = 3; - MCHBAR8(0xf10) |= 1 << 1; + mchbar_write16(0xc14, 0); + mchbar_write16(0xc20, 0); + mchbar_write32(0xfc0, 0x001f00fd); + mchbar_setbits32(0xfc0, 3 << 25); + mchbar_setbits32(0xfc0, 1 << 11); + mchbar_write8(0xfb0, 3); + mchbar_setbits8(0xf10, 1 << 1); if (fsb == FSB_CLOCK_667MHz) { - MCHBAR16(0xc3a) = 0xea6; - MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x0e; + mchbar_write16(0xc3a, 0x0ea6); + mchbar_clrsetbits8(0xc16, 0x7f, 0x0e); } else if (fsb == FSB_CLOCK_800MHz) { - MCHBAR16(0xc3a) = 0x1194; - MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x10; + mchbar_write16(0xc3a, 0x1194); + mchbar_clrsetbits8(0xc16, 0x7f, 0x10); } else if (fsb == FSB_CLOCK_1067MHz) { - MCHBAR16(0xc3a) = 0x1777; - MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x15; + mchbar_write16(0xc3a, 0x1777); + mchbar_clrsetbits8(0xc16, 0x7f, 0x15); } - MCHBAR8(0xfb8) = 3; + mchbar_write8(0xfb8, 3); if (fsb == FSB_CLOCK_667MHz) - MCHBAR16(0xc38) = 0x0ea6; + mchbar_write16(0xc38, 0x0ea6); else if (fsb == FSB_CLOCK_800MHz) - MCHBAR16(0xc38) = 0x1194; + mchbar_write16(0xc38, 0x1194); else if (fsb == FSB_CLOCK_1067MHz) - MCHBAR16(0xc38) = 0x1777; - MCHBAR8(0xf10) |= 1 << 5; - MCHBAR16(0xc16) |= 3 << 12; - MCHBAR32(0xf60) = 0x01030419; + mchbar_write16(0xc38, 0x1777); + mchbar_setbits8(0xf10, 1 << 5); + mchbar_setbits16(0xc16, 3 << 12); + mchbar_write32(0xf60, 0x01030419); if (fsb == FSB_CLOCK_667MHz) { - MCHBAR32(0xf00) = 0x00000600; - MCHBAR32(0xf04) = 0x00001d80; + mchbar_write32(0xf00, 0x00000600); + mchbar_write32(0xf04, 0x00001d80); } else if (fsb == FSB_CLOCK_800MHz) { - MCHBAR32(0xf00) = 0x00000700; - MCHBAR32(0xf04) = 0x00002380; + mchbar_write32(0xf00, 0x00000700); + mchbar_write32(0xf04, 0x00002380); } else if (fsb == FSB_CLOCK_1067MHz) { - MCHBAR32(0xf00) = 0x00000900; - MCHBAR32(0xf04) = 0x00002e80; + mchbar_write32(0xf00, 0x00000900); + mchbar_write32(0xf04, 0x00002e80); } - MCHBAR16(0xf08) = 0x730f; + mchbar_write16(0xf08, 0x730f); if (fsb == FSB_CLOCK_667MHz) - MCHBAR16(0xf0c) = 0x0b96; + mchbar_write16(0xf0c, 0x0b96); else if (fsb == FSB_CLOCK_800MHz) - MCHBAR16(0xf0c) = 0x0c99; + mchbar_write16(0xf0c, 0x0c99); else if (fsb == FSB_CLOCK_1067MHz) - MCHBAR16(0xf0c) = 0x10a4; - MCHBAR32(0xf80) |= 1 << 31; + mchbar_write16(0xf0c, 0x10a4); + mchbar_setbits32(0xf80, 1 << 31); - MCHBAR32(0x40) = (MCHBAR32(0x40) & ~(0x3f << 24)) | - (sysinfo->cores == 4) ? (1 << 24) : 0; + mchbar_write32(0x40, (mchbar_read32(0x40) & ~(0x3f << 24)) | + (sysinfo->cores == 4) ? (1 << 24) : 0); - MCHBAR32(0x40) &= ~(1 << 19); - MCHBAR32(0x40) |= 1 << 13; - MCHBAR32(0x40) |= 1 << 21; - MCHBAR32(0x40) |= 1 << 9; + mchbar_clrbits32(0x40, 1 << 19); + mchbar_setbits32(0x40, 1 << 13); + mchbar_setbits32(0x40, 1 << 21); + mchbar_setbits32(0x40, 1 << 9); if (stepping > STEPPING_B1) { if (fsb != FSB_CLOCK_1067MHz) { - MCHBAR32(0x70) |= 1 << 30; + mchbar_setbits32(0x70, 1 << 30); } else { - MCHBAR32(0x70) &= ~(1 << 30); + mchbar_clrbits32(0x70, 1 << 30); } } if (stepping < STEPPING_B1) - MCHBAR32(0x70) |= 1 << 29; + mchbar_setbits32(0x70, 1 << 29); else - MCHBAR32(0x70) &= ~(1 << 29); + mchbar_clrbits32(0x70, 1 << 29); if (stepping > STEPPING_B1) { - MCHBAR32(0x70) |= 1 << 28; - MCHBAR32(0x70) |= 1 << 25; + mchbar_setbits32(0x70, 1 << 28); + mchbar_setbits32(0x70, 1 << 25); } if (stepping > STEPPING_B0) { if (fsb != FSB_CLOCK_667MHz) - MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)) | (1 << 21); + mchbar_clrsetbits32(0x70, 3 << 21, 1 << 21); else - MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)); + mchbar_clrbits32(0x70, 3 << 21); } if (stepping > STEPPING_B2) - MCHBAR32(0x44) |= 1 << 30; - MCHBAR32(0x44) |= 1 << 31; + mchbar_setbits32(0x44, 1 << 30); + mchbar_setbits32(0x44, 1 << 31); if (sysinfo->cores == 2) - MCHBAR32(0x44) |= 1 << 26; - MCHBAR32(0x44) |= 1 << 21; - MCHBAR32(0x44) = (MCHBAR32(0x44) & ~(3 << 24)) | (2 << 24); - MCHBAR32(0x44) |= 1 << 5; - MCHBAR32(0x44) |= 1 << 4; - MCHBAR32(0x90) = (MCHBAR32(0x90) & ~7) | 4; - MCHBAR32(0x94) |= 1 << 29; - MCHBAR32(0x94) |= 1 << 11; + mchbar_setbits32(0x44, 1 << 26); + mchbar_setbits32(0x44, 1 << 21); + mchbar_clrsetbits32(0x44, 3 << 24, 2 << 24); + mchbar_setbits32(0x44, 1 << 5); + mchbar_setbits32(0x44, 1 << 4); + mchbar_clrsetbits32(0x90, 7, 4); + mchbar_setbits32(0x94, 1 << 29); + mchbar_setbits32(0x94, 1 << 11); if (stepping < STEPPING_B0) - MCHBAR32(0x94) = (MCHBAR32(0x94) & ~(3 << 19)) | (2 << 19); + mchbar_clrsetbits32(0x94, 3 << 19, 2 << 19); if (stepping > STEPPING_B2) - MCHBAR32(0x94) |= 1 << 21; - MCHBAR8(0xb00) &= ~1; - MCHBAR8(0xb00) |= 1 << 7; + mchbar_setbits32(0x94, 1 << 21); + mchbar_clrbits8(0xb00, 1 << 0); + mchbar_setbits8(0xb00, 1 << 7); if (fsb != FSB_CLOCK_1067MHz) - MCHBAR8(0x75) |= 1 << 6; + mchbar_setbits8(0x75, 1 << 6); else - MCHBAR8(0x75) &= 1 << 1; - MCHBAR8(0x77) |= 3; + mchbar_clrbits8(0x75, ~(1 << 1)); + mchbar_setbits8(0x77, 3); if (stepping >= STEPPING_B1) - MCHBAR8(0x77) |= 1 << 2; + mchbar_setbits8(0x77, 1 << 2); if (stepping > STEPPING_B2) - MCHBAR8(0x77) |= 1 << 4; - if (MCHBAR16(0x90) & 0x100) - MCHBAR8(0x90) &= ~(7 << 4); + mchbar_setbits8(0x77, 1 << 4); + if (mchbar_read16(0x90) & (1 << 8)) + mchbar_clrbits8(0x90, 7 << 4); if (stepping >= STEPPING_B0) - MCHBAR8(0xd0) |= 1 << 1; - MCHBAR8(0xbd8) |= 3 << 2; + mchbar_setbits8(0xd0, 1 << 1); + mchbar_setbits8(0xbd8, 3 << 2); if (stepping >= STEPPING_B3) - MCHBAR32(0x70) |= 1 << 0; - MCHBAR32(0x70) |= 1 << 3; + mchbar_setbits32(0x70, 1 << 0); + mchbar_setbits32(0x70, 1 << 3); if (stepping >= STEPPING_B0) - MCHBAR32(0x70) &= ~(1 << 16); + mchbar_clrbits32(0x70, 1 << 16); else - MCHBAR32(0x70) |= 1 << 16; + mchbar_setbits32(0x70, 1 << 16); if (stepping >= STEPPING_B3) - MCHBAR8(0xc14) |= 1 << 1; + mchbar_setbits8(0xc14, 1 << 1); if (stepping >= STEPPING_B1) - MCHBAR16(0xffc) = (MCHBAR16(0xffc) & ~0x7ff) | 0x7c0; - MCHBAR16(0x48) = (MCHBAR16(0x48) & ~(0xff << 2)) | (0xaa << 2); + mchbar_clrsetbits16(0xffc, 0x7ff, 0x7c0); + mchbar_clrsetbits16(0x48, 0xff << 2, 0xaa << 2); if (stepping == STEPPING_CONVERSION_A1) { - MCHBAR16(0x40) |= 1 << 12; - MCHBAR32(0x94) |= 3 << 22; + mchbar_setbits16(0x40, 1 << 12); + mchbar_setbits32(0x94, 3 << 22); } const int cpu_supports_super_lfm = rdmsr(MSR_EXTENDED_CONFIG).lo & (1 << 27); if ((stepping >= STEPPING_B0) && cpu_supports_super_lfm) { - MCHBAR16(CLKCFG_MCHBAR) &= ~(1 << 7); - MCHBAR16(CLKCFG_MCHBAR) |= 1 << 14; + mchbar_clrbits16(CLKCFG_MCHBAR, 1 << 7); + mchbar_setbits16(CLKCFG_MCHBAR, 1 << 14); } else { - MCHBAR16(CLKCFG_MCHBAR) &= ~(1 << 14); - MCHBAR16(CLKCFG_MCHBAR) |= 1 << 7; - MCHBAR32(0x44) &= ~(1 << 31); /* Was set above. */ + mchbar_clrbits16(CLKCFG_MCHBAR, 1 << 14); + mchbar_setbits16(CLKCFG_MCHBAR, 1 << 7); + mchbar_clrbits32(0x44, 1 << 31); /* Was set above. */ } if ((sysinfo->gfx_type != GMCH_PM45) && do_freq_scaling_cfg && @@ -268,5 +265,5 @@ void init_pm(const sysinfo_t *const sysinfo, int do_freq_scaling_cfg) /* This has to be the last write to CLKCFG. */ if ((fsb == FSB_CLOCK_1067MHz) && (memclk == MEM_CLOCK_667MT)) - MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 17); + mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 17); } diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index f9d7c8fbed..d990497a46 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -348,7 +348,7 @@ static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config) static fsb_clock_t read_fsb_clock(void) { - switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { + switch (mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { case 6: return FSB_CLOCK_1067MHz; case 2: @@ -666,9 +666,9 @@ static void collect_dimm_config(sysinfo_t *const sysinfo) static void reset_on_bad_warmboot(void) { /* Check self refresh channel status. */ - const u32 reg = MCHBAR32(PMSTS_MCHBAR); + const u32 reg = mchbar_read32(PMSTS_MCHBAR); /* Clear status bits. R/WC */ - MCHBAR32(PMSTS_MCHBAR) = reg; + mchbar_write32(PMSTS_MCHBAR, reg); if ((reg & PMSTS_WARM_RESET) && !(reg & PMSTS_BOTH_SELFREFRESH)) { printk(BIOS_INFO, "DRAM was not in self refresh " "during warm boot, reset required.\n"); @@ -678,62 +678,62 @@ static void reset_on_bad_warmboot(void) static void set_system_memory_frequency(const timings_t *const timings) { - MCHBAR16(CLKCFG_MCHBAR + 0x60) &= ~(1 << 15); - MCHBAR16(CLKCFG_MCHBAR + 0x48) &= ~(1 << 15); + mchbar_clrbits16(CLKCFG_MCHBAR + 0x60, 1 << 15); + mchbar_clrbits16(CLKCFG_MCHBAR + 0x48, 1 << 15); /* Calculate wanted frequency setting. */ const int want_freq = 6 - timings->mem_clock; /* Read current memory frequency. */ - const u32 clkcfg = MCHBAR32(CLKCFG_MCHBAR); + const u32 clkcfg = mchbar_read32(CLKCFG_MCHBAR); int cur_freq = (clkcfg & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT; if (0 == cur_freq) { /* Try memory frequency from scratchpad. */ printk(BIOS_DEBUG, "Reading current memory frequency from scratchpad.\n"); - cur_freq = (MCHBAR16(SSKPD_MCHBAR) & SSKPD_CLK_MASK) >> SSKPD_CLK_SHIFT; + cur_freq = (mchbar_read16(SSKPD_MCHBAR) & SSKPD_CLK_MASK) >> SSKPD_CLK_SHIFT; } if (cur_freq != want_freq) { printk(BIOS_DEBUG, "Changing memory frequency: old %x, new %x.\n", cur_freq, want_freq); /* When writing new frequency setting, reset, then set update bit. */ - MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(CLKCFG_UPDATE | CLKCFG_MEMCLK_MASK)) | - (want_freq << CLKCFG_MEMCLK_SHIFT); - MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~CLKCFG_MEMCLK_MASK) | - (want_freq << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE; + mchbar_clrsetbits32(CLKCFG_MCHBAR, CLKCFG_UPDATE | CLKCFG_MEMCLK_MASK, + want_freq << CLKCFG_MEMCLK_SHIFT); + mchbar_clrsetbits32(CLKCFG_MCHBAR, CLKCFG_MEMCLK_MASK, + want_freq << CLKCFG_MEMCLK_SHIFT | CLKCFG_UPDATE); /* Reset update bit. */ - MCHBAR32(CLKCFG_MCHBAR) &= ~CLKCFG_UPDATE; + mchbar_clrbits32(CLKCFG_MCHBAR, CLKCFG_UPDATE); } if ((timings->fsb_clock == FSB_CLOCK_1067MHz) && (timings->mem_clock == MEM_CLOCK_667MT)) { - MCHBAR32(CLKCFG_MCHBAR + 0x16) = 0x000030f0; - MCHBAR32(CLKCFG_MCHBAR + 0x64) = 0x000050c1; - - MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 12)) | (1 << 17); - MCHBAR32(CLKCFG_MCHBAR) |= (1 << 17) | (1 << 12); - MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 12); - - MCHBAR32(CLKCFG_MCHBAR + 0x04) = 0x9bad1f1f; - MCHBAR8(CLKCFG_MCHBAR + 0x08) = 0xf4; - MCHBAR8(CLKCFG_MCHBAR + 0x0a) = 0x43; - MCHBAR8(CLKCFG_MCHBAR + 0x0c) = 0x10; - MCHBAR8(CLKCFG_MCHBAR + 0x0d) = 0x80; - MCHBAR32(CLKCFG_MCHBAR + 0x50) = 0x0b0e151b; - MCHBAR8(CLKCFG_MCHBAR + 0x54) = 0xb4; - MCHBAR8(CLKCFG_MCHBAR + 0x55) = 0x10; - MCHBAR8(CLKCFG_MCHBAR + 0x56) = 0x08; - - MCHBAR32(CLKCFG_MCHBAR) |= (1 << 10); - MCHBAR32(CLKCFG_MCHBAR) |= (1 << 11); - MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 10); - MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 11); - } - - MCHBAR32(CLKCFG_MCHBAR + 0x48) |= 0x3f << 24; + mchbar_write32(CLKCFG_MCHBAR + 0x16, 0x000030f0); + mchbar_write32(CLKCFG_MCHBAR + 0x64, 0x000050c1); + + mchbar_clrsetbits32(CLKCFG_MCHBAR, 1 << 12, 1 << 17); + mchbar_setbits32(CLKCFG_MCHBAR, 1 << 17 | 1 << 12); + mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 12); + + mchbar_write32(CLKCFG_MCHBAR + 0x04, 0x9bad1f1f); + mchbar_write8(CLKCFG_MCHBAR + 0x08, 0xf4); + mchbar_write8(CLKCFG_MCHBAR + 0x0a, 0x43); + mchbar_write8(CLKCFG_MCHBAR + 0x0c, 0x10); + mchbar_write8(CLKCFG_MCHBAR + 0x0d, 0x80); + mchbar_write32(CLKCFG_MCHBAR + 0x50, 0x0b0e151b); + mchbar_write8(CLKCFG_MCHBAR + 0x54, 0xb4); + mchbar_write8(CLKCFG_MCHBAR + 0x55, 0x10); + mchbar_write8(CLKCFG_MCHBAR + 0x56, 0x08); + + mchbar_setbits32(CLKCFG_MCHBAR, 1 << 10); + mchbar_setbits32(CLKCFG_MCHBAR, 1 << 11); + mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 10); + mchbar_clrbits32(CLKCFG_MCHBAR, 1 << 11); + } + + mchbar_setbits32(CLKCFG_MCHBAR + 0x48, 0x3f << 24); } int raminit_read_vco_index(void) { - switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { + switch (mchbar_read8(HPLLVCO_MCHBAR) & 0x7) { case VCO_2666: return 0; case VCO_3200: @@ -778,10 +778,10 @@ static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo) return; } - MCHBAR16(0x119e) = 0xa800; - MCHBAR16(0x11c0) = (MCHBAR16(0x11c0) & ~0xff00) | (0x01 << 8); - MCHBAR16(0x119e) = 0xb800; - MCHBAR8(0x0f10) |= 1 << 7; + mchbar_write16(0x119e, 0xa800); + mchbar_clrsetbits16(0x11c0, 0xff << 8, 0x01 << 8); + mchbar_write16(0x119e, 0xb800); + mchbar_setbits8(0x0f10, 1 << 7); /* Read VCO. */ const int vco_idx = raminit_read_vco_index(); @@ -820,32 +820,32 @@ static void configure_dram_control_mode(const timings_t *const timings, const di FOR_EACH_CHANNEL(ch) { unsigned int mchbar = CxDRC0_MCHBAR(ch); - u32 cxdrc = MCHBAR32(mchbar); + u32 cxdrc = mchbar_read32(mchbar); cxdrc &= ~CxDRC0_RANKEN_MASK; FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) cxdrc |= CxDRC0_RANKEN(r); cxdrc = (cxdrc & ~CxDRC0_RMS_MASK) | /* Always 7.8us for DDR3: */ CxDRC0_RMS_78US; - MCHBAR32(mchbar) = cxdrc; + mchbar_write32(mchbar, cxdrc); mchbar = CxDRC1_MCHBAR(ch); - cxdrc = MCHBAR32(mchbar); + cxdrc = mchbar_read32(mchbar); cxdrc |= CxDRC1_NOTPOP_MASK; FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) cxdrc &= ~CxDRC1_NOTPOP(r); cxdrc |= CxDRC1_MUSTWR; - MCHBAR32(mchbar) = cxdrc; + mchbar_write32(mchbar, cxdrc); mchbar = CxDRC2_MCHBAR(ch); - cxdrc = MCHBAR32(mchbar); + cxdrc = mchbar_read32(mchbar); cxdrc |= CxDRC2_NOTPOP_MASK; FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) cxdrc &= ~CxDRC2_NOTPOP(r); cxdrc |= CxDRC2_MUSTWR; if (timings->mem_clock == MEM_CLOCK_1067MT) cxdrc |= CxDRC2_CLK1067MT; - MCHBAR32(mchbar) = cxdrc; + mchbar_write32(mchbar, cxdrc); } } @@ -855,61 +855,61 @@ static void rcomp_initialization(const stepping_t stepping, const int sff) if (sff) die("SFF platform unsupported in RCOMP initialization.\n"); /* Values are for DDR3. */ - MCHBAR8(0x6ac) &= ~0x0f; - MCHBAR8(0x6b0) = 0x55; - MCHBAR8(0x6ec) &= ~0x0f; - MCHBAR8(0x6f0) = 0x66; - MCHBAR8(0x72c) &= ~0x0f; - MCHBAR8(0x730) = 0x66; - MCHBAR8(0x76c) &= ~0x0f; - MCHBAR8(0x770) = 0x66; - MCHBAR8(0x7ac) &= ~0x0f; - MCHBAR8(0x7b0) = 0x66; - MCHBAR8(0x7ec) &= ~0x0f; - MCHBAR8(0x7f0) = 0x66; - MCHBAR8(0x86c) &= ~0x0f; - MCHBAR8(0x870) = 0x55; - MCHBAR8(0x8ac) &= ~0x0f; - MCHBAR8(0x8b0) = 0x66; + mchbar_clrbits8(0x6ac, 0x0f); + mchbar_write8(0x6b0, 0x55); + mchbar_clrbits8(0x6ec, 0x0f); + mchbar_write8(0x6f0, 0x66); + mchbar_clrbits8(0x72c, 0x0f); + mchbar_write8(0x730, 0x66); + mchbar_clrbits8(0x76c, 0x0f); + mchbar_write8(0x770, 0x66); + mchbar_clrbits8(0x7ac, 0x0f); + mchbar_write8(0x7b0, 0x66); + mchbar_clrbits8(0x7ec, 0x0f); + mchbar_write8(0x7f0, 0x66); + mchbar_clrbits8(0x86c, 0x0f); + mchbar_write8(0x870, 0x55); + mchbar_clrbits8(0x8ac, 0x0f); + mchbar_write8(0x8b0, 0x66); /* ODT multiplier bits. */ - MCHBAR32(0x04d0) = (MCHBAR32(0x04d0) & ~((7 << 3) | (7 << 0))) | (2 << 3) | (2 << 0); + mchbar_clrsetbits32(0x04d0, 7 << 3 | 7 << 0, 2 << 3 | 2 << 0); /* Perform RCOMP calibration for DDR3. */ raminit_rcomp_calibration(stepping); /* Run initial RCOMP. */ - MCHBAR32(0x418) |= 1 << 17; - MCHBAR32(0x40c) &= ~(1 << 23); - MCHBAR32(0x41c) &= ~((1 << 7) | (1 << 3)); - MCHBAR32(0x400) |= 1; - while (MCHBAR32(0x400) & 1) {} + mchbar_setbits32(0x418, 1 << 17); + mchbar_clrbits32(0x40c, 1 << 23); + mchbar_clrbits32(0x41c, 1 << 7 | 1 << 3); + mchbar_setbits32(0x400, 1); + while (mchbar_read32(0x400) & 1) {} /* Run second RCOMP. */ - MCHBAR32(0x40c) |= 1 << 19; - MCHBAR32(0x400) |= 1; - while (MCHBAR32(0x400) & 1) {} + mchbar_setbits32(0x40c, 1 << 19); + mchbar_setbits32(0x400, 1); + while (mchbar_read32(0x400) & 1) {} /* Cleanup and start periodic RCOMP. */ - MCHBAR32(0x40c) &= ~(1 << 19); - MCHBAR32(0x40c) |= 1 << 23; - MCHBAR32(0x418) &= ~(1 << 17); - MCHBAR32(0x41c) |= (1 << 7) | (1 << 3); - MCHBAR32(0x400) |= (1 << 1); + mchbar_clrbits32(0x40c, 1 << 19); + mchbar_setbits32(0x40c, 1 << 23); + mchbar_clrbits32(0x418, 1 << 17); + mchbar_setbits32(0x41c, 1 << 7 | 1 << 3); + mchbar_setbits32(0x400, 1 << 1); } static void dram_powerup(const int resume) { udelay(200); - MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21); + mchbar_clrsetbits32(CLKCFG_MCHBAR, 1 << 3, 3 << 21); if (!resume) { - MCHBAR32(0x1434) |= (1 << 10); + mchbar_setbits32(0x1434, 1 << 10); udelay(1); } - MCHBAR32(0x1434) |= (1 << 6); + mchbar_setbits32(0x1434, 1 << 6); if (!resume) { udelay(1); - MCHBAR32(0x1434) |= (1 << 9); - MCHBAR32(0x1434) &= ~(1 << 10); + mchbar_setbits32(0x1434, 1 << 9); + mchbar_clrbits32(0x1434, 1 << 10); udelay(500); } } @@ -921,7 +921,7 @@ static void dram_program_timings(const timings_t *const timings) int i; FOR_EACH_CHANNEL(i) { - u32 reg = MCHBAR32(CxDRT0_MCHBAR(i)); + u32 reg = mchbar_read32(CxDRT0_MCHBAR(i)); const int btb_wtp = timings->tWL + burst_length/2 + timings->tWR; const int btb_wtr = timings->tWL + burst_length/2 + tWTR; reg = (reg & ~(CxDRT0_BtB_WtP_MASK | CxDRT0_BtB_WtR_MASK)) | @@ -936,17 +936,17 @@ static void dram_program_timings(const timings_t *const timings) } reg = (reg & ~(0x7 << 5)) | (3 << 5); reg = (reg & ~(0x7 << 0)) | (1 << 0); - MCHBAR32(CxDRT0_MCHBAR(i)) = reg; + mchbar_write32(CxDRT0_MCHBAR(i), reg); - reg = MCHBAR32(CxDRT1_MCHBAR(i)); + reg = mchbar_read32(CxDRT1_MCHBAR(i)); reg = (reg & ~(0x03 << 28)) | ((tRTP & 0x03) << 28); reg = (reg & ~(0x1f << 21)) | ((timings->tRAS & 0x1f) << 21); reg = (reg & ~(0x07 << 10)) | (((timings->tRRD - 2) & 0x07) << 10); reg = (reg & ~(0x07 << 5)) | (((timings->tRCD - 2) & 0x07) << 5); reg = (reg & ~(0x07 << 0)) | (((timings->tRP - 2) & 0x07) << 0); - MCHBAR32(CxDRT1_MCHBAR(i)) = reg; + mchbar_write32(CxDRT1_MCHBAR(i), reg); - reg = MCHBAR32(CxDRT2_MCHBAR(i)); + reg = mchbar_read32(CxDRT2_MCHBAR(i)); reg = (reg & ~(0x1f << 17)) | ((timings->tFAW & 0x1f) << 17); if (timings->mem_clock != MEM_CLOCK_1067MT) { reg = (reg & ~(0x7 << 12)) | (0x2 << 12); @@ -956,17 +956,17 @@ static void dram_program_timings(const timings_t *const timings) reg = (reg & ~(0xf << 6)) | (0xc << 6); } reg = (reg & ~(0x1f << 0)) | (0x13 << 0); - MCHBAR32(CxDRT2_MCHBAR(i)) = reg; + mchbar_write32(CxDRT2_MCHBAR(i), reg); - reg = MCHBAR32(CxDRT3_MCHBAR(i)); + reg = mchbar_read32(CxDRT3_MCHBAR(i)); reg |= 0x3 << 28; reg = (reg & ~(0x03 << 26)); reg = (reg & ~(0x07 << 23)) | (((timings->CAS - 3) & 0x07) << 23); reg = (reg & ~(0xff << 13)) | ((timings->tRFC & 0xff) << 13); reg = (reg & ~(0x07 << 0)) | (((timings->tWL - 2) & 0x07) << 0); - MCHBAR32(CxDRT3_MCHBAR(i)) = reg; + mchbar_write32(CxDRT3_MCHBAR(i), reg); - reg = MCHBAR32(CxDRT4_MCHBAR(i)); + reg = mchbar_read32(CxDRT4_MCHBAR(i)); static const u8 timings_by_clock[4][3] = { /* 333MHz 400MHz 533MHz 667MT 800MT 1067MT */ @@ -980,9 +980,9 @@ static void dram_program_timings(const timings_t *const timings) reg = (reg & ~(0x3ff << 17)) | (timings_by_clock[1][clk_idx] << 17); reg = (reg & ~(0x03f << 10)) | (timings_by_clock[2][clk_idx] << 10); reg = (reg & ~(0x1ff << 0)) | (timings_by_clock[3][clk_idx] << 0); - MCHBAR32(CxDRT4_MCHBAR(i)) = reg; + mchbar_write32(CxDRT4_MCHBAR(i), reg); - reg = MCHBAR32(CxDRT5_MCHBAR(i)); + reg = mchbar_read32(CxDRT5_MCHBAR(i)); if (timings->mem_clock == MEM_CLOCK_1067MT) reg = (reg & ~(0xf << 28)) | (0x8 << 28); reg = (reg & ~(0x00f << 22)) | ((burst_length/2 + timings->CAS + 2) << 22); @@ -990,12 +990,12 @@ static void dram_program_timings(const timings_t *const timings) reg = (reg & ~(0x00f << 4)) | ((timings->CAS - 2) << 4); reg = (reg & ~(0x003 << 2)) | (0x001 << 2); reg = (reg & ~(0x003 << 0)); - MCHBAR32(CxDRT5_MCHBAR(i)) = reg; + mchbar_write32(CxDRT5_MCHBAR(i), reg); - reg = MCHBAR32(CxDRT6_MCHBAR(i)); + reg = mchbar_read32(CxDRT6_MCHBAR(i)); reg = (reg & ~(0xffff << 16)) | (0x066a << 16); /* always 7.8us refresh rate for DDR3 */ reg |= (1 << 2); - MCHBAR32(CxDRT6_MCHBAR(i)) = reg; + mchbar_write32(CxDRT6_MCHBAR(i), reg); } } @@ -1006,16 +1006,16 @@ static void dram_program_banks(const dimminfo_t *const dimms) FOR_EACH_CHANNEL(ch) { const int tRPALL = dimms[ch].banks == 8; - u32 reg = MCHBAR32(CxDRT1_MCHBAR(ch)) & ~(0x01 << 15); + u32 reg = mchbar_read32(CxDRT1_MCHBAR(ch)) & ~(0x01 << 15); IF_CHANNEL_POPULATED(dimms, ch) reg |= tRPALL << 15; - MCHBAR32(CxDRT1_MCHBAR(ch)) = reg; + mchbar_write32(CxDRT1_MCHBAR(ch), reg); - reg = MCHBAR32(CxDRA_MCHBAR(ch)) & ~CxDRA_BANKS_MASK; + reg = mchbar_read32(CxDRA_MCHBAR(ch)) & ~CxDRA_BANKS_MASK; FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { reg |= CxDRA_BANKS(r, dimms[ch].banks); } - MCHBAR32(CxDRA_MCHBAR(ch)) = reg; + mchbar_write32(CxDRA_MCHBAR(ch), reg); } } @@ -1025,7 +1025,7 @@ static void odt_setup(const timings_t *const timings, const int sff) int ch; FOR_EACH_CHANNEL(ch) { - u32 reg = MCHBAR32(CxODT_HIGH(ch)); + u32 reg = mchbar_read32(CxODT_HIGH(ch)); if (sff && (timings->mem_clock != MEM_CLOCK_1067MT)) reg &= ~(0x3 << (61 - 32)); else @@ -1041,9 +1041,9 @@ static void odt_setup(const timings_t *const timings, const int sff) reg = (reg & ~(0xf << (36 - 32))) | (( 1 + timings->CAS) << (36 - 32)); } reg = (reg & ~(0xf << (32 - 32))) | (0x7 << (32 - 32)); - MCHBAR32(CxODT_HIGH(ch)) = reg; + mchbar_write32(CxODT_HIGH(ch), reg); - reg = MCHBAR32(CxODT_LOW(ch)); + reg = mchbar_read32(CxODT_LOW(ch)); reg = (reg & ~(0x7 << 28)) | (0x2 << 28); reg = (reg & ~(0x3 << 22)) | (0x2 << 22); reg = (reg & ~(0x7 << 12)) | (0x2 << 12); @@ -1059,27 +1059,27 @@ static void odt_setup(const timings_t *const timings, const int sff) reg = (reg & ~0x7) | 0x5; break; } - MCHBAR32(CxODT_LOW(ch)) = reg; + mchbar_write32(CxODT_LOW(ch), reg); } } static void misc_settings(const timings_t *const timings, const stepping_t stepping) { - MCHBAR32(0x1260) = (MCHBAR32(0x1260) & ~((1 << 24) | 0x1f)) | timings->tRD; - MCHBAR32(0x1360) = (MCHBAR32(0x1360) & ~((1 << 24) | 0x1f)) | timings->tRD; - - MCHBAR8(0x1268) = (MCHBAR8(0x1268) & ~(0xf)) | timings->tWL; - MCHBAR8(0x1368) = (MCHBAR8(0x1368) & ~(0xf)) | timings->tWL; - MCHBAR8(0x12a0) = (MCHBAR8(0x12a0) & ~(0xf)) | 0xa; - MCHBAR8(0x13a0) = (MCHBAR8(0x13a0) & ~(0xf)) | 0xa; - - MCHBAR32(0x218) = (MCHBAR32(0x218) & ~((7 << 29) | (7 << 25) | (3 << 22) | (3 << 10))) | - (4 << 29) | (3 << 25) | (0 << 22) | (1 << 10); - MCHBAR32(0x220) = (MCHBAR32(0x220) & ~(7 << 16)) | (1 << 21) | (1 << 16); - MCHBAR32(0x224) = (MCHBAR32(0x224) & ~(7 << 8)) | (3 << 8); + mchbar_clrsetbits32(0x1260, 1 << 24 | 0x1f, timings->tRD); + mchbar_clrsetbits32(0x1360, 1 << 24 | 0x1f, timings->tRD); + + mchbar_clrsetbits8(0x1268, 0xf, timings->tWL); + mchbar_clrsetbits8(0x1368, 0xf, timings->tWL); + mchbar_clrsetbits8(0x12a0, 0xf, 0xa); + mchbar_clrsetbits8(0x13a0, 0xf, 0xa); + + mchbar_clrsetbits32(0x218, 7 << 29 | 7 << 25 | 3 << 22 | 3 << 10, + 4 << 29 | 3 << 25 | 0 << 22 | 1 << 10); + mchbar_clrsetbits32(0x220, 7 << 16, 1 << 21 | 1 << 16); + mchbar_clrsetbits32(0x224, 7 << 8, 3 << 8); if (stepping >= STEPPING_B1) - MCHBAR8(0x234) |= (1 << 3); + mchbar_setbits8(0x234, 1 << 3); } static void clock_crossing_setup(const fsb_clock_t fsb, @@ -1107,10 +1107,10 @@ static void clock_crossing_setup(const fsb_clock_t fsb, }; const u32 *data = values_from_fsb_and_mem[fsb][ddr3clock]; - MCHBAR32(0x0208) = data[3]; - MCHBAR32(0x020c) = data[2]; + mchbar_write32(0x0208, data[3]); + mchbar_write32(0x020c, data[2]); if (((fsb == FSB_CLOCK_1067MHz) || (fsb == FSB_CLOCK_800MHz)) && (ddr3clock == MEM_CLOCK_667MT)) - MCHBAR32(0x0210) = data[1]; + mchbar_write32(0x0210, data[1]); static const u32 from_fsb_and_mem[][3] = { /* DDR3-1067 DDR3-800 DDR3-667 */ @@ -1121,10 +1121,10 @@ static void clock_crossing_setup(const fsb_clock_t fsb, FOR_EACH_CHANNEL(ch) { const unsigned int mchbar = 0x1258 + (ch * 0x0100); if ((fsb == FSB_CLOCK_1067MHz) && (ddr3clock == MEM_CLOCK_800MT) && CHANNEL_IS_CARDF(dimms, ch)) - MCHBAR32(mchbar) = 0x08040120; + mchbar_write32(mchbar, 0x08040120); else - MCHBAR32(mchbar) = from_fsb_and_mem[fsb][ddr3clock]; - MCHBAR32(mchbar + 4) = 0x00000000; + mchbar_write32(mchbar, from_fsb_and_mem[fsb][ddr3clock]); + mchbar_write32(mchbar + 4, 0); } } @@ -1136,9 +1136,9 @@ static void vc1_program_timings(const fsb_clock_t fsb) /* FSB 800MHz */ { 0x14, 0x00f000f0 }, /* FSB 667MHz */ { 0x10, 0x00c000c0 }, }; - EPBAR8(EPVC1ITC) = timings_by_fsb[fsb][0]; - EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1]; - EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1]; + epbar_write8(EPVC1ITC, timings_by_fsb[fsb][0]); + epbar_write32(EPVC1IST + 0, timings_by_fsb[fsb][1]); + epbar_write32(EPVC1IST + 4, timings_by_fsb[fsb][1]); } #define DEFAULT_PCI_MMIO_SIZE 2048 @@ -1190,13 +1190,13 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode } reg |= CxDRBy_BOUND_MB(r+1, base); - MCHBAR32(CxDRBy_MCHBAR(ch, r)) = reg; + mchbar_write32(CxDRBy_MCHBAR(ch, r), reg); } } /* Program page size (CxDRA). */ FOR_EACH_CHANNEL(ch) { - u32 reg = MCHBAR32(CxDRA_MCHBAR(ch)) & ~CxDRA_PAGESIZE_MASK; + u32 reg = mchbar_read32(CxDRA_MCHBAR(ch)) & ~CxDRA_PAGESIZE_MASK; FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { /* Fixed page size for pre-jedec config. */ const unsigned int page_size = /* dimm page size in bytes */ @@ -1204,7 +1204,7 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode reg |= CxDRA_PAGESIZE(r, log2(page_size)); /* deferred to f5_27: reg |= CxDRA_BANKS(r, dimms[ch].banks); */ } - MCHBAR32(CxDRA_MCHBAR(ch)) = reg; + mchbar_write32(CxDRA_MCHBAR(ch), reg); } /* Calculate memory mapping, all values in MB. */ @@ -1271,16 +1271,16 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode switch (mode) { case CHANNEL_MODE_SINGLE: printk(BIOS_DEBUG, "Memory configured in single-channel mode.\n"); - MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; + mchbar_clrbits32(DCC_MCHBAR, DCC_INTERLEAVED); break; case CHANNEL_MODE_DUAL_ASYNC: printk(BIOS_DEBUG, "Memory configured in dual-channel asymmetric mode.\n"); - MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; + mchbar_clrbits32(DCC_MCHBAR, DCC_INTERLEAVED); break; case CHANNEL_MODE_DUAL_INTERLEAVED: printk(BIOS_DEBUG, "Memory configured in dual-channel interleaved mode.\n"); - MCHBAR32(DCC_MCHBAR) &= ~(DCC_NO_CHANXOR | (1 << 9)); - MCHBAR32(DCC_MCHBAR) |= DCC_INTERLEAVED; + mchbar_clrbits32(DCC_MCHBAR, DCC_NO_CHANXOR | 1 << 9); + mchbar_setbits32(DCC_MCHBAR, DCC_INTERLEAVED); break; } @@ -1300,7 +1300,7 @@ static void prejedec_memory_map(const dimminfo_t *const dimms, channel_mode_t mo mode = CHANNEL_MODE_DUAL_ASYNC; program_memory_map(dimms, mode, 1, 0); - MCHBAR32(DCC_MCHBAR) |= DCC_NO_CHANXOR; + mchbar_setbits32(DCC_MCHBAR, DCC_NO_CHANXOR); } static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, @@ -1320,21 +1320,21 @@ static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, if ((1 == ch) && (!CHANNEL_IS_POPULATED(dimms, 0) || (cardF[0] != cardF[1]))) mixed = 4 << 11; const unsigned int b = 0x14b0 + (ch * 0x0100); - MCHBAR32(b+0x1c) = (MCHBAR32(b+0x1c) & ~(7 << 11)) | - ((( cardF[ch])?1:0) << 11) | mixed; - MCHBAR32(b+0x18) = (MCHBAR32(b+0x18) & ~(7 << 11)) | mixed; - MCHBAR32(b+0x14) = (MCHBAR32(b+0x14) & ~(7 << 11)) | - (((!clk1067 && !cardF[ch])?0:1) << 11) | mixed; - MCHBAR32(b+0x10) = (MCHBAR32(b+0x10) & ~(7 << 11)) | - ((( clk1067 && !cardF[ch])?1:0) << 11) | mixed; - MCHBAR32(b+0x0c) = (MCHBAR32(b+0x0c) & ~(7 << 11)) | - ((( cardF[ch])?3:2) << 11) | mixed; - MCHBAR32(b+0x08) = (MCHBAR32(b+0x08) & ~(7 << 11)) | - (2 << 11) | mixed; - MCHBAR32(b+0x04) = (MCHBAR32(b+0x04) & ~(7 << 11)) | - (((!clk1067 && !cardF[ch])?2:3) << 11) | mixed; - MCHBAR32(b+0x00) = (MCHBAR32(b+0x00) & ~(7 << 11)) | - ((( clk1067 && !cardF[ch])?3:2) << 11) | mixed; + mchbar_write32(b + 0x1c, (mchbar_read32(b + 0x1c) & ~(7 << 11)) | + ((( cardF[ch])?1:0) << 11) | mixed); + mchbar_write32(b + 0x18, (mchbar_read32(b + 0x18) & ~(7 << 11)) | mixed); + mchbar_write32(b + 0x14, (mchbar_read32(b + 0x14) & ~(7 << 11)) | + (((!clk1067 && !cardF[ch])?0:1) << 11) | mixed); + mchbar_write32(b + 0x10, (mchbar_read32(b + 0x10) & ~(7 << 11)) | + ((( clk1067 && !cardF[ch])?1:0) << 11) | mixed); + mchbar_write32(b + 0x0c, (mchbar_read32(b + 0x0c) & ~(7 << 11)) | + ((( cardF[ch])?3:2) << 11) | mixed); + mchbar_write32(b + 0x08, (mchbar_read32(b + 0x08) & ~(7 << 11)) | + (2 << 11) | mixed); + mchbar_write32(b + 0x04, (mchbar_read32(b + 0x04) & ~(7 << 11)) | + (((!clk1067 && !cardF[ch])?2:3) << 11) | mixed); + mchbar_write32(b + 0x00, (mchbar_read32(b + 0x00) & ~(7 << 11)) | + ((( clk1067 && !cardF[ch])?3:2) << 11) | mixed); } } static void ddr3_write_io_init(const mem_clock_t ddr3clock, @@ -1392,16 +1392,16 @@ static void ddr3_write_io_init(const mem_clock_t ddr3clock, const u32 *const data = (ddr3clock != MEM_CLOCK_1067MT) ? ddr3_667_800_by_stepping_ddr3_and_card[a1step][2 - ddr3clock][cardF[ch]] : ddr3_1067_by_channel_and_card[ch][cardF[ch]]; - MCHBAR32(CxWRTy_MCHBAR(ch, 0)) = data[0]; - MCHBAR32(CxWRTy_MCHBAR(ch, 1)) = data[1]; - MCHBAR32(CxWRTy_MCHBAR(ch, 2)) = data[2]; - MCHBAR32(CxWRTy_MCHBAR(ch, 3)) = data[3]; + mchbar_write32(CxWRTy_MCHBAR(ch, 0), data[0]); + mchbar_write32(CxWRTy_MCHBAR(ch, 1), data[1]); + mchbar_write32(CxWRTy_MCHBAR(ch, 2), data[2]); + mchbar_write32(CxWRTy_MCHBAR(ch, 3), data[3]); } - MCHBAR32(0x1490) = 0x00e70067; - MCHBAR32(0x1494) = 0x000d8000; - MCHBAR32(0x1590) = 0x00e70067; - MCHBAR32(0x1594) = 0x000d8000; + mchbar_write32(0x1490, 0x00e70067); + mchbar_write32(0x1494, 0x000d8000); + mchbar_write32(0x1590, 0x00e70067); + mchbar_write32(0x1594, 0x000d8000); } static void ddr3_read_io_init(const mem_clock_t ddr3clock, const dimminfo_t *const dimms, @@ -1413,7 +1413,7 @@ static void ddr3_read_io_init(const mem_clock_t ddr3clock, u32 addr, tmp; const unsigned int base = 0x14b0 + (ch * 0x0100); for (addr = base + 0x1c; addr >= base; addr -= 4) { - tmp = MCHBAR32(addr); + tmp = mchbar_read32(addr); tmp &= ~((3 << 25) | (1 << 8) | (7 << 16) | (0xf << 20) | (1 << 27)); tmp |= (1 << 27); switch (ddr3clock) { @@ -1432,7 +1432,7 @@ static void ddr3_read_io_init(const mem_clock_t ddr3clock, default: die("Wrong clock"); } - MCHBAR32(addr) = tmp; + mchbar_write32(addr, tmp); } } } @@ -1448,12 +1448,12 @@ static void memory_io_init(const mem_clock_t ddr3clock, die("Stepping <B1 unsupported in " "system-memory i/o initialization.\n"); - tmp = MCHBAR32(0x1400); + tmp = mchbar_read32(0x1400); tmp &= ~(3<<13); tmp |= (1<<9) | (1<<13); - MCHBAR32(0x1400) = tmp; + mchbar_write32(0x1400, tmp); - tmp = MCHBAR32(0x140c); + tmp = mchbar_read32(0x140c); tmp &= ~(0xff | (1<<11) | (1<<12) | (1<<16) | (1<<18) | (1<<27) | (0xf<<28)); tmp |= (1<<7) | (1<<11) | (1<<16); @@ -1468,11 +1468,11 @@ static void memory_io_init(const mem_clock_t ddr3clock, tmp |= 8 << 28; break; } - MCHBAR32(0x140c) = tmp; + mchbar_write32(0x140c, tmp); - MCHBAR32(0x1440) &= ~1; + mchbar_clrbits32(0x1440, 1); - tmp = MCHBAR32(0x1414); + tmp = mchbar_read32(0x1414); tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); tmp |= (3<<11); switch (ddr3clock) { @@ -1486,15 +1486,15 @@ static void memory_io_init(const mem_clock_t ddr3clock, tmp |= (4 << 24) | (4 << 16); break; } - MCHBAR32(0x1414) = tmp; + mchbar_write32(0x1414, tmp); - MCHBAR32(0x1418) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); + mchbar_clrbits32(0x1418, 1 << 3 | 1 << 11 | 1 << 19 | 1 << 27); - MCHBAR32(0x141c) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); + mchbar_clrbits32(0x141c, 1 << 3 | 1 << 11 | 1 << 19 | 1 << 27); - MCHBAR32(0x1428) |= 1<<14; + mchbar_setbits32(0x1428, 1 << 14); - tmp = MCHBAR32(0x142c); + tmp = mchbar_read32(0x142c); tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24)); tmp |= (0x3 << 20) | (5 << 24); switch (ddr3clock) { @@ -1508,26 +1508,26 @@ static void memory_io_init(const mem_clock_t ddr3clock, tmp |= (4 << 8) | 0x7; break; } - MCHBAR32(0x142c) = tmp; + mchbar_write32(0x142c, tmp); - tmp = MCHBAR32(0x400); + tmp = mchbar_read32(0x400); tmp &= ~((3 << 4) | (3 << 16) | (3 << 30)); tmp |= (2 << 4) | (2 << 16); - MCHBAR32(0x400) = tmp; + mchbar_write32(0x400, tmp); - MCHBAR32(0x404) &= ~(0xf << 20); + mchbar_clrbits32(0x404, 0xf << 20); - MCHBAR32(0x40c) &= ~(1 << 6); + mchbar_clrbits32(0x40c, 1 << 6); - tmp = MCHBAR32(0x410); + tmp = mchbar_read32(0x410); tmp &= ~(7 << 28); tmp |= 2 << 28; - MCHBAR32(0x410) = tmp; + mchbar_write32(0x410, tmp); - tmp = MCHBAR32(0x41c); + tmp = mchbar_read32(0x41c); tmp &= ~0x77; tmp |= 0x11; - MCHBAR32(0x41c) = tmp; + mchbar_write32(0x41c, tmp); ddr3_select_clock_mux(ddr3clock, dimms, stepping); @@ -1543,16 +1543,16 @@ static void jedec_init(const timings_t *const timings, die("tWR value unsupported in Jedec initialization.\n"); /* Pre-jedec settings */ - MCHBAR32(0x40) |= (1 << 1); - MCHBAR32(0x230) |= (3 << 1); - MCHBAR32(0x238) |= (3 << 24); - MCHBAR32(0x23c) |= (3 << 24); + mchbar_setbits32(0x40, 1 << 1); + mchbar_setbits32(0x230, 3 << 1); + mchbar_setbits32(0x238, 3 << 24); + mchbar_setbits32(0x23c, 3 << 24); /* Normal write pointer operation */ - MCHBAR32(0x14f0) |= (1 << 9); - MCHBAR32(0x15f0) |= (1 << 9); + mchbar_setbits32(0x14f0, 1 << 9); + mchbar_setbits32(0x15f0, 1 << 9); - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; + mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP); pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2)); @@ -1577,15 +1577,15 @@ static void jedec_init(const timings_t *const timings, Mirrored ranks aren't taken into account here. */ const u32 rankaddr = raminit_get_rank_addr(ch, r); printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); + mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(2)); read32((u32 *)(rankaddr | WL)); - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3); + mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(3)); read32((u32 *)rankaddr); - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1); + mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(1)); read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS)); - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; + mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG); read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED)); - MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; + mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG); read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED)); } } @@ -1593,51 +1593,51 @@ static void jedec_init(const timings_t *const timings, static void ddr3_calibrate_zq(void) { udelay(2); - u32 tmp = MCHBAR32(DCC_MCHBAR); + u32 tmp = mchbar_read32(DCC_MCHBAR); tmp &= ~(7 << 16); tmp |= (5 << 16); /* ZQ calibration mode */ - MCHBAR32(DCC_MCHBAR) = tmp; + mchbar_write32(DCC_MCHBAR, tmp); - MCHBAR32(CxDRT6_MCHBAR(0)) |= (1 << 3); - MCHBAR32(CxDRT6_MCHBAR(1)) |= (1 << 3); + mchbar_setbits32(CxDRT6_MCHBAR(0), 1 << 3); + mchbar_setbits32(CxDRT6_MCHBAR(1), 1 << 3); udelay(1); - MCHBAR32(CxDRT6_MCHBAR(0)) &= ~(1 << 3); - MCHBAR32(CxDRT6_MCHBAR(1)) &= ~(1 << 3); + mchbar_clrbits32(CxDRT6_MCHBAR(0), 1 << 3); + mchbar_clrbits32(CxDRT6_MCHBAR(1), 1 << 3); - MCHBAR32(DCC_MCHBAR) |= (7 << 16); /* Normal operation */ + mchbar_setbits32(DCC_MCHBAR, 7 << 16); /* Normal operation */ } static void post_jedec_sequence(const int cores) { const int quadcore = cores == 4; - MCHBAR32(0x0040) &= ~(1 << 1); - MCHBAR32(0x0230) &= ~(3 << 1); - MCHBAR32(0x0230) |= 1 << 15; - MCHBAR32(0x0230) &= ~(1 << 19); - MCHBAR32(0x1250) = 0x6c4; - MCHBAR32(0x1350) = 0x6c4; - MCHBAR32(0x1254) = 0x871a066d; - MCHBAR32(0x1354) = 0x871a066d; - MCHBAR32(0x0238) |= 1 << 26; - MCHBAR32(0x0238) &= ~(3 << 24); - MCHBAR32(0x0238) |= 1 << 23; - MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 20)) | (3 << 20); - MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 17)) | (6 << 17); - MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 14)) | (6 << 14); - MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 11)) | (6 << 11); - MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 8)) | (6 << 8); - MCHBAR32(0x023c) &= ~(3 << 24); - MCHBAR32(0x023c) &= ~(1 << 23); - MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 20)) | (3 << 20); - MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 17)) | (6 << 17); - MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 14)) | (6 << 14); - MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 11)) | (6 << 11); - MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 8)) | (6 << 8); + mchbar_clrbits32(0x0040, 1 << 1); + mchbar_clrbits32(0x0230, 3 << 1); + mchbar_setbits32(0x0230, 1 << 15); + mchbar_clrbits32(0x0230, 1 << 19); + mchbar_write32(0x1250, 0x6c4); + mchbar_write32(0x1350, 0x6c4); + mchbar_write32(0x1254, 0x871a066d); + mchbar_write32(0x1354, 0x871a066d); + mchbar_setbits32(0x0238, 1 << 26); + mchbar_clrbits32(0x0238, 3 << 24); + mchbar_setbits32(0x0238, 1 << 23); + mchbar_clrsetbits32(0x0238, 7 << 20, 3 << 20); + mchbar_clrsetbits32(0x0238, 7 << 17, 6 << 17); + mchbar_clrsetbits32(0x0238, 7 << 14, 6 << 14); + mchbar_clrsetbits32(0x0238, 7 << 11, 6 << 11); + mchbar_clrsetbits32(0x0238, 7 << 8, 6 << 8); + mchbar_clrbits32(0x023c, 3 << 24); + mchbar_clrbits32(0x023c, 1 << 23); + mchbar_clrsetbits32(0x023c, 7 << 20, 3 << 20); + mchbar_clrsetbits32(0x023c, 7 << 17, 6 << 17); + mchbar_clrsetbits32(0x023c, 7 << 14, 6 << 14); + mchbar_clrsetbits32(0x023c, 7 << 11, 6 << 11); + mchbar_clrsetbits32(0x023c, 7 << 8, 6 << 8); if (quadcore) { - MCHBAR32(0xb14) |= (0xbfbf << 16); + mchbar_setbits32(0xb14, 0xbfbf << 16); } } @@ -1648,13 +1648,13 @@ static void dram_optimizations(const timings_t *const timings, FOR_EACH_POPULATED_CHANNEL(dimms, ch) { const unsigned int mchbar = CxDRC1_MCHBAR(ch); - u32 cxdrc1 = MCHBAR32(mchbar); + u32 cxdrc1 = mchbar_read32(mchbar); cxdrc1 &= ~CxDRC1_SSDS_MASK; if (dimms[ch].ranks == 1) cxdrc1 |= CxDRC1_SS; else cxdrc1 |= CxDRC1_DS; - MCHBAR32(mchbar) = cxdrc1; + mchbar_write32(mchbar, cxdrc1); } } @@ -1670,22 +1670,23 @@ u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank) rank = 3; /* Highest rank per channel */ channel--; } - const u32 reg = MCHBAR32(CxDRBy_MCHBAR(channel, rank)); + const u32 reg = mchbar_read32(CxDRBy_MCHBAR(channel, rank)); /* Bound is in 32MB. */ return ((reg & CxDRBy_BOUND_MASK(rank)) >> CxDRBy_BOUND_SHIFT(rank)) << 25; } -void raminit_reset_readwrite_pointers(void) { - MCHBAR32(0x1234) |= (1 << 6); - MCHBAR32(0x1234) &= ~(1 << 6); - MCHBAR32(0x1334) |= (1 << 6); - MCHBAR32(0x1334) &= ~(1 << 6); - MCHBAR32(0x14f0) &= ~(1 << 9); - MCHBAR32(0x14f0) |= (1 << 9); - MCHBAR32(0x14f0) |= (1 << 10); - MCHBAR32(0x15f0) &= ~(1 << 9); - MCHBAR32(0x15f0) |= (1 << 9); - MCHBAR32(0x15f0) |= (1 << 10); +void raminit_reset_readwrite_pointers(void) +{ + mchbar_setbits32(0x1234, 1 << 6); + mchbar_clrbits32(0x1234, 1 << 6); + mchbar_setbits32(0x1334, 1 << 6); + mchbar_clrbits32(0x1334, 1 << 6); + mchbar_clrbits32(0x14f0, 1 << 9); + mchbar_setbits32(0x14f0, 1 << 9); + mchbar_setbits32(0x14f0, 1 << 10); + mchbar_clrbits32(0x15f0, 1 << 9); + mchbar_setbits32(0x15f0, 1 << 9); + mchbar_setbits32(0x15f0, 1 << 10); } void raminit(sysinfo_t *const sysinfo, const int s3resume) @@ -1713,10 +1714,10 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Program DRAM type. */ switch (sysinfo->spd_type) { case DDR2: - MCHBAR8(0x1434) |= (1 << 7); + mchbar_setbits8(0x1434, 1 << 7); break; case DDR3: - MCHBAR8(0x1434) |= (3 << 0); + mchbar_setbits8(0x1434, 3 << 0); break; } @@ -1739,7 +1740,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) dram_program_banks(dimms); /* Enable DRAM clock pairs for populated DIMMs. */ FOR_EACH_POPULATED_CHANNEL(dimms, ch) - MCHBAR32(CxDCLKDIS_MCHBAR(ch)) |= CxDCLKDIS_ENABLE; + mchbar_setbits32(CxDCLKDIS_MCHBAR(ch), CxDCLKDIS_ENABLE); /* Enable On-Die Termination. */ odt_setup(timings, sysinfo->sff); @@ -1763,7 +1764,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) post_jedec_sequence(sysinfo->cores); /* Announce normal operation, initialization completed. */ - MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19); + mchbar_setbits32(DCC_MCHBAR, 0x7 << 16 | 0x1 << 19); pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, 1 << 2); @@ -1778,12 +1779,10 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Perform receive-enable calibration. */ raminit_receive_enable_calibration(timings, dimms); /* Lend clock values from receive-enable calibration. */ - MCHBAR32(CxDRT5_MCHBAR(0)) = - (MCHBAR32(CxDRT5_MCHBAR(0)) & ~(0xf0)) | - ((((MCHBAR32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4); - MCHBAR32(CxDRT5_MCHBAR(1)) = - (MCHBAR32(CxDRT5_MCHBAR(1)) & ~(0xf0)) | - ((((MCHBAR32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4); + mchbar_clrsetbits32(CxDRT5_MCHBAR(0), 0xf0, + (((mchbar_read32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4); + mchbar_clrsetbits32(CxDRT5_MCHBAR(1), 0xf0, + (((mchbar_read32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4); /* Perform read/write training for high clock rate. */ if (timings->mem_clock == MEM_CLOCK_1067MT) { diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c index 94da2dc589..aef863f05a 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -153,11 +153,11 @@ static void lookup_and_write(const int a1step, /* Write 4 32-bit registers, 4 values each. */ for (i = row; i < row + 16; i += 4) { - MCHBAR32(mchbar) = - ((ddr3_lut[a1step][i + 0][col] & 0x3f) << 0) | - ((ddr3_lut[a1step][i + 1][col] & 0x3f) << 8) | - ((ddr3_lut[a1step][i + 2][col] & 0x3f) << 16) | - ((ddr3_lut[a1step][i + 3][col] & 0x3f) << 24); + mchbar_write32(mchbar, + (ddr3_lut[a1step][i + 0][col] & 0x3f) << 0 | + (ddr3_lut[a1step][i + 1][col] & 0x3f) << 8 | + (ddr3_lut[a1step][i + 2][col] & 0x3f) << 16 | + (ddr3_lut[a1step][i + 3][col] & 0x3f) << 24); mchbar += 4; } } @@ -175,33 +175,33 @@ void raminit_rcomp_calibration(const stepping_t stepping) { for (i = 0; i < 2 * 6 * 2; ++i) ((char *)lut_idx)[i] = -1; - MCHBAR32(0x400) |= (1 << 2); - MCHBAR32(0x418) |= (1 << 17); - MCHBAR32(0x40c) &= ~(1 << 23); - MCHBAR32(0x41c) &= ~((1 << 7) | (1 << 3)); - MCHBAR32(0x400) |= 1; + mchbar_setbits32(0x400, 1 << 2); + mchbar_setbits32(0x418, 1 << 17); + mchbar_clrbits32(0x40c, 1 << 23); + mchbar_clrbits32(0x41c, 1 << 7 | 1 << 3); + mchbar_setbits32(0x400, 1 << 0); /* Read lookup indices. */ for (i = 0; i < 12; ++i) { do { - MCHBAR32(0x400) |= (1 << 3); + mchbar_setbits32(0x400, 1 << 3); udelay(10); - MCHBAR32(0x400) &= ~(1 << 3); - } while ((MCHBAR32(0x530) & 0x7) != 0x4); - u32 reg = MCHBAR32(0x400); + mchbar_clrbits32(0x400, 1 << 3); + } while ((mchbar_read32(0x530) & 0x7) != 0x4); + u32 reg = mchbar_read32(0x400); const unsigned int group = (reg >> 13) & 0x7; const unsigned int channel = (reg >> 12) & 0x1; if (group > 5) break; - reg = MCHBAR32(0x518); + reg = mchbar_read32(0x518); lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f; lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f; } /* Cleanup? */ - MCHBAR32(0x400) |= (1 << 3); + mchbar_setbits32(0x400, 1 << 3); udelay(10); - MCHBAR32(0x400) &= ~(1 << 3); - MCHBAR32(0x400) &= ~(1 << 2); + mchbar_clrbits32(0x400, 1 << 3); + mchbar_clrbits32(0x400, 1 << 2); /* Check for consistency. */ for (i = 0; i < 2 * 6 * 2; ++i) { diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index e8d719fca6..544c523b32 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -77,10 +77,10 @@ static int program_read_timing(const int ch, const int lane, if (normalize_read_timing(timing) < 0) return -1; - u32 reg = MCHBAR32(CxRDTy_MCHBAR(ch, lane)); + u32 reg = mchbar_read32(CxRDTy_MCHBAR(ch, lane)); reg &= ~(CxRDTy_T_MASK | CxRDTy_P_MASK); reg |= CxRDTy_T(timing->t) | CxRDTy_P(timing->p); - MCHBAR32(CxRDTy_MCHBAR(ch, lane)) = reg; + mchbar_write32(CxRDTy_MCHBAR(ch, lane), reg); return 0; } @@ -164,7 +164,7 @@ static void read_training_per_lane(const int channel, const int lane, { read_timing_t lower, upper; - MCHBAR32(CxRDTy_MCHBAR(channel, lane)) |= 3 << 25; + mchbar_setbits32(CxRDTy_MCHBAR(channel, lane), 3 << 25); /*** Search lower bound. ***/ @@ -227,7 +227,7 @@ static void read_training_store_results(void) /* Store one timing pair in one byte each. */ FOR_EACH_CHANNEL(ch) { for (i = 0; i < 8; ++i) { - const u32 bl_reg = MCHBAR32(CxRDTy_MCHBAR(ch, i)); + const u32 bl_reg = mchbar_read32(CxRDTy_MCHBAR(ch, i)); bytes[(ch * 8) + i] = (((bl_reg & CxRDTy_T_MASK) >> CxRDTy_T_SHIFT) << 4) | @@ -253,10 +253,10 @@ static void read_training_restore_results(void) for (i = 0; i < 8; ++i) { const int t = bytes[(ch * 8) + i] >> 4; const int p = bytes[(ch * 8) + i] & 7; - u32 bl_reg = MCHBAR32(CxRDTy_MCHBAR(ch, i)); + u32 bl_reg = mchbar_read32(CxRDTy_MCHBAR(ch, i)); bl_reg &= ~(CxRDTy_T_MASK | CxRDTy_P_MASK); bl_reg |= (3 << 25) | CxRDTy_T(t) | CxRDTy_P(p); - MCHBAR32(CxRDTy_MCHBAR(ch, i)) = bl_reg; + mchbar_write32(CxRDTy_MCHBAR(ch, i), bl_reg); printk(BIOS_DEBUG, "Restored timings for byte lane " "%d on channel %d: %d.%d\n", i, ch, t, p); } @@ -395,11 +395,11 @@ static int program_write_timing(const int ch, const int group, (t <= d_bounds[memclk1067][0]) ? CxWRTy_BELOW_D : ((t > d_bounds[memclk1067][1]) ? CxWRTy_ABOVE_D : 0); - u32 reg = MCHBAR32(CxWRTy_MCHBAR(ch, group)); + u32 reg = mchbar_read32(CxWRTy_MCHBAR(ch, group)); reg &= ~(CxWRTy_T_MASK | CxWRTy_P_MASK | CxWRTy_F_MASK); reg &= ~CxWRTy_D_MASK; reg |= CxWRTy_T(t) | CxWRTy_P(p) | CxWRTy_F(f) | d; - MCHBAR32(CxWRTy_MCHBAR(ch, group)) = reg; + mchbar_write32(CxWRTy_MCHBAR(ch, group), reg); return 0; } @@ -409,10 +409,10 @@ static int write_training_test(const address_bunch_t *const addresses, { int i, ret = 0; - const u32 mmarb0 = MCHBAR32(0x0220); - const u8 wrcctl = MCHBAR8(0x0218); - MCHBAR32(0x0220) |= 0xf << 28; - MCHBAR8(0x0218) |= 0x1 << 4; + const u32 mmarb0 = mchbar_read32(0x0220); + const u8 wrcctl = mchbar_read8(0x0218); + mchbar_setbits32(0x0220, 0xf << 28); + mchbar_setbits8(0x0218, 0x1 << 4); for (i = 0; i < addresses->count; ++i) { const unsigned int addr = addresses->addr[i]; @@ -423,7 +423,7 @@ static int write_training_test(const address_bunch_t *const addresses, write32((u32 *)(addr + off + 4), pattern); } - MCHBAR8(0x78) |= 1; + mchbar_setbits8(0x78, 1); for (off = 0; off < 640; off += 8) { const u32 good = write_training_schedule[off >> 3]; @@ -438,8 +438,8 @@ static int write_training_test(const address_bunch_t *const addresses, ret = 1; _bad_timing_out: - MCHBAR32(0x0220) = mmarb0; - MCHBAR8(0x0218) = wrcctl; + mchbar_write32(0x0220, mmarb0); + mchbar_write8(0x0218, wrcctl); return ret; } @@ -510,7 +510,7 @@ static void write_training_per_group(const int ch, const int group, /*** Search lower bound. ***/ /* Start at -1f from current values. */ - const u32 reg = MCHBAR32(CxWRTy_MCHBAR(ch, group)); + const u32 reg = mchbar_read32(CxWRTy_MCHBAR(ch, group)); lower.t = (reg >> 12) & 0xf; lower.p = (reg >> 8) & 0x7; lower.f = ((reg >> 2) & 0x3) - 1; @@ -592,7 +592,7 @@ static void write_training_store_results(void) /* We could save six bytes by putting all F values in two bytes. */ FOR_EACH_CHANNEL(ch) { for (i = 0; i < 4; ++i) { - const u32 reg = MCHBAR32(CxWRTy_MCHBAR(ch, i)); + const u32 reg = mchbar_read32(CxWRTy_MCHBAR(ch, i)); bytes[(ch * 8) + (i * 2)] = (((reg & CxWRTy_T_MASK) >> CxWRTy_T_SHIFT) << 4) | diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 6d95b3401b..0b1c789ef9 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -110,29 +110,28 @@ static void program_timing(int channel, int group, /* C value is per channel. */ unsigned int mchbar = CxDRT3_MCHBAR(channel); - MCHBAR32(mchbar) = (MCHBAR32(mchbar) & ~CxDRT3_C_MASK) | - CxDRT3_C(timing->c); + mchbar_clrsetbits32(mchbar, CxDRT3_C_MASK, CxDRT3_C(timing->c)); /* All other per group. */ mchbar = CxRECy_MCHBAR(channel, group); - u32 reg = MCHBAR32(mchbar); + u32 reg = mchbar_read32(mchbar); reg &= ~CxRECy_TIMING_MASK; reg |= CxRECy_T(timing->t) | CxRECy_P(timing->p) | CxRECy_PH(timing->ph) | CxRECy_PM(timing->pre); - MCHBAR32(mchbar) = reg; + mchbar_write32(mchbar, reg); } static int read_dqs_level(const int channel, const int lane) { unsigned int mchbar = 0x14f0 + (channel * 0x0100); - MCHBAR32(mchbar) &= ~(1 << 9); - MCHBAR32(mchbar) |= (1 << 9); + mchbar_clrbits32(mchbar, 1 << 9); + mchbar_setbits32(mchbar, 1 << 9); /* Read from this channel. */ read32((u32 *)raminit_get_rank_addr(channel, 0)); mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); - return MCHBAR32(mchbar) & (1 << 30); + return mchbar_read32(mchbar) & (1 << 30); } static void find_dqs_low(const int channel, const int group, @@ -272,22 +271,22 @@ void raminit_receive_enable_calibration(const timings_t *const timings, unsigned int group; for (group = 0; group < 4; ++group) { const unsigned int mchbar = CxRECy_MCHBAR(ch, group); - u32 reg = MCHBAR32(mchbar); + u32 reg = mchbar_read32(mchbar); reg &= ~((3 << 16) | (1 << 8) | 3); reg |= (map[group][0] - group); reg |= (map[group][1] - group - 1) << 16; - MCHBAR32(mchbar) = reg; + mchbar_write32(mchbar, reg); } } - MCHBAR32(0x12a4) |= 1 << 31; - MCHBAR32(0x13a4) |= 1 << 31; - MCHBAR32(0x14f0) = (MCHBAR32(0x14f0) & ~(3 << 9)) | (1 << 9); - MCHBAR32(0x15f0) = (MCHBAR32(0x15f0) & ~(3 << 9)) | (1 << 9); + mchbar_setbits32(0x12a4, 1 << 31); + mchbar_setbits32(0x13a4, 1 << 31); + mchbar_clrsetbits32(0x14f0, 3 << 9, 1 << 9); + mchbar_clrsetbits32(0x15f0, 3 << 9, 1 << 9); receive_enable_calibration(timings, dimms); - MCHBAR32(0x12a4) &= ~(1 << 31); - MCHBAR32(0x13a4) &= ~(1 << 31); + mchbar_clrbits32(0x12a4, 1 << 31); + mchbar_clrbits32(0x13a4, 1 << 31); raminit_reset_readwrite_pointers(); } diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c index 22aaee62d8..b87380a076 100644 --- a/src/northbridge/intel/gm45/romstage.c +++ b/src/northbridge/intel/gm45/romstage.c @@ -50,13 +50,13 @@ void mainboard_romstage_entry(void) reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); - if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { + if ((mchbar_read16(SSKPD_MCHBAR) == 0xcafe) && !(reg16 & (1 << 9))) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); gm45_early_reset(); } /* ASPM related setting, set early by original BIOS. */ - DMIBAR16(0x204) &= ~(3 << 10); + dmibar_clrbits16(0x204, 3 << 10); /* Check for S3 resume. */ s3resume = southbridge_detect_s3_resume(); @@ -89,7 +89,7 @@ void mainboard_romstage_entry(void) gm45_late_init(sysinfo.stepping); i82801ix_dmi_poll_vc1(); - MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; + mchbar_write16(SSKPD_MCHBAR, 0xcafe); init_iommu(); diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index a5d9820e71..3be674aae2 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -15,65 +15,65 @@ void raminit_thermal(const sysinfo_t *sysinfo) const chip_width_t width = sysinfo->dimms[x].chip_width; const chip_capacity_t size = sysinfo->dimms[x].chip_capacity; if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x16)) { - MCHBAR32(CxDTPEW(x)) = 0x0d0b0403; - MCHBAR32(CxDTPEW(x)+4) = 0x060d; - MCHBAR32(CxDTAEW(x)) = 0x2d0b221a; - MCHBAR32(CxDTAEW(x)+4) = 0xc779956e; + mchbar_write32(CxDTPEW(x), 0x0d0b0403); + mchbar_write32(CxDTPEW(x) + 4, 0x060d); + mchbar_write32(CxDTAEW(x), 0x2d0b221a); + mchbar_write32(CxDTAEW(x) + 4, 0xc779956e); } else if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x8)) { - MCHBAR32(CxDTPEW(x)) = 0x06040101; - MCHBAR32(CxDTPEW(x)+4) = 0x0506; + mchbar_write32(CxDTPEW(x), 0x06040101); + mchbar_write32(CxDTPEW(x) + 4, 0x0506); if (size == CHIP_CAP_2G) - MCHBAR32(CxDTAEW(x)) = 0xa1071416; + mchbar_write32(CxDTAEW(x), 0xa1071416); else - MCHBAR32(CxDTAEW(x)) = 0x1a071416; - MCHBAR32(CxDTAEW(x)+4) = 0x7246643f; + mchbar_write32(CxDTAEW(x), 0x1a071416); + mchbar_write32(CxDTAEW(x) + 4, 0x7246643f); } else if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x16)) { - MCHBAR32(CxDTPEW(x)) = 0x06030100; - MCHBAR32(CxDTPEW(x)+4) = 0x0506; - MCHBAR32(CxDTAEW(x)) = 0x3e081714; - MCHBAR32(CxDTAEW(x)+4) = 0xbb79a171; + mchbar_write32(CxDTPEW(x), 0x06030100); + mchbar_write32(CxDTPEW(x) + 4, 0x0506); + mchbar_write32(CxDTAEW(x), 0x3e081714); + mchbar_write32(CxDTAEW(x) + 4, 0xbb79a171); } else if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x8)) { if (size <= CHIP_CAP_512M) - MCHBAR32(CxDTPEW(x)) = 0x05050101; + mchbar_write32(CxDTPEW(x), 0x05050101); else - MCHBAR32(CxDTPEW(x)) = 0x05060101; - MCHBAR32(CxDTPEW(x)+4) = 0x0503; + mchbar_write32(CxDTPEW(x), 0x05060101); + mchbar_write32(CxDTPEW(x) + 4, 0x0503); if (size == CHIP_CAP_2G) { - MCHBAR32(CxDTAEW(x)) = 0x57051010; - MCHBAR32(CxDTAEW(x)+4) = 0x5fd15dde; + mchbar_write32(CxDTAEW(x), 0x57051010); + mchbar_write32(CxDTAEW(x) + 4, 0x5fd15dde); } else if (size == CHIP_CAP_1G) { - MCHBAR32(CxDTAEW(x)) = 0x3306130e; - MCHBAR32(CxDTAEW(x)+4) = 0x5763485d; + mchbar_write32(CxDTAEW(x), 0x3306130e); + mchbar_write32(CxDTAEW(x) + 4, 0x5763485d); } else if (size <= CHIP_CAP_512M) { - MCHBAR32(CxDTAEW(x)) = 0x1e08170d; - MCHBAR32(CxDTAEW(x)+4) = 0x502f3827; + mchbar_write32(CxDTAEW(x), 0x1e08170d); + mchbar_write32(CxDTAEW(x) + 4, 0x502f3827); } } else if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x16)) { - MCHBAR32(CxDTPEW(x)) = 0x02000000; - MCHBAR32(CxDTPEW(x)+4) = 0x0402; - MCHBAR32(CxDTAEW(x)) = 0x46061111; - MCHBAR32(CxDTAEW(x)+4) = 0xb579a772; + mchbar_write32(CxDTPEW(x), 0x02000000); + mchbar_write32(CxDTPEW(x) + 4, 0x0402); + mchbar_write32(CxDTAEW(x), 0x46061111); + mchbar_write32(CxDTAEW(x) + 4, 0xb579a772); } else if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x8)) { - MCHBAR32(CxDTPEW(x)) = 0x04070101; - MCHBAR32(CxDTPEW(x)+4) = 0x0501; + mchbar_write32(CxDTPEW(x), 0x04070101); + mchbar_write32(CxDTPEW(x) + 4, 0x0501); if (size == CHIP_CAP_2G) { - MCHBAR32(CxDTAEW(x)) = 0x32040e0d; - MCHBAR32(CxDTAEW(x)+4) = 0x55ff59ff; + mchbar_write32(CxDTAEW(x), 0x32040e0d); + mchbar_write32(CxDTAEW(x) + 4, 0x55ff59ff); } else if (size == CHIP_CAP_1G) { - MCHBAR32(CxDTAEW(x)) = 0x3f05120a; - MCHBAR32(CxDTAEW(x)+4) = 0x49713a6c; + mchbar_write32(CxDTAEW(x), 0x3f05120a); + mchbar_write32(CxDTAEW(x) + 4, 0x49713a6c); } else if (size <= CHIP_CAP_512M) { - MCHBAR32(CxDTAEW(x)) = 0x20081808; - MCHBAR32(CxDTAEW(x)+4) = 0x3f23221b; + mchbar_write32(CxDTAEW(x), 0x20081808); + mchbar_write32(CxDTAEW(x) + 4, 0x3f23221b); } } @@ -81,95 +81,95 @@ void raminit_thermal(const sysinfo_t *sysinfo) if (sysinfo->selected_timings.channel_mode == CHANNEL_MODE_DUAL_INTERLEAVED) { if (freq == MEM_CLOCK_1067MT) { - MCHBAR32(CxGTEW(x)) = 0xc8f81717; + mchbar_write32(CxGTEW(x), 0xc8f81717); } else if (freq == MEM_CLOCK_800MT) { - MCHBAR32(CxGTEW(x)) = 0x96ba1717; + mchbar_write32(CxGTEW(x), 0x96ba1717); } else if (freq == MEM_CLOCK_667MT) { - MCHBAR32(CxGTEW(x)) = 0x7d9b1717; + mchbar_write32(CxGTEW(x), 0x7d9b1717); } } else { if (freq == MEM_CLOCK_1067MT) { - MCHBAR32(CxGTEW(x)) = 0x53661717; + mchbar_write32(CxGTEW(x), 0x53661717); } else if (freq == MEM_CLOCK_800MT) { - MCHBAR32(CxGTEW(x)) = 0x886e1717; + mchbar_write32(CxGTEW(x), 0x886e1717); } else if (freq == MEM_CLOCK_667MT) { - MCHBAR32(CxGTEW(x)) = 0x38621717; + mchbar_write32(CxGTEW(x), 0x38621717); } } } // always? - MCHBAR32(CxDTC(0)) = 0x00004020; - MCHBAR32(CxDTC(1)) = 0x00004020; - MCHBAR32(CxGTC(0)) = 0x00304848; - MCHBAR32(CxGTC(1)) = 0x00304848; + mchbar_write32(CxDTC(0), 0x00004020); + mchbar_write32(CxDTC(1), 0x00004020); + mchbar_write32(CxGTC(0), 0x00304848); + mchbar_write32(CxGTC(1), 0x00304848); /* enable thermal sensors */ u32 tmp; - tmp = MCHBAR32(0x1290) & 0xfff8; - MCHBAR32(0x1290) = tmp | 0xa4810007; - tmp = MCHBAR32(0x1390) & 0xfff8; - MCHBAR32(0x1390) = tmp | 0xa4810007; - tmp = MCHBAR32(0x12b4) & 0xfff8; - MCHBAR32(0x12b4) = tmp | 0xa2810007; - tmp = MCHBAR32(0x13b4) & 0xfff8; - MCHBAR32(0x13b4) = tmp | 0xa2810007; - MCHBAR8(0x1070) = 1; - MCHBAR8(0x1080) = 6; + tmp = mchbar_read32(0x1290) & 0xfff8; + mchbar_write32(0x1290, tmp | 0xa4810007); + tmp = mchbar_read32(0x1390) & 0xfff8; + mchbar_write32(0x1390, tmp | 0xa4810007); + tmp = mchbar_read32(0x12b4) & 0xfff8; + mchbar_write32(0x12b4, tmp | 0xa2810007); + tmp = mchbar_read32(0x13b4) & 0xfff8; + mchbar_write32(0x13b4, tmp | 0xa2810007); + mchbar_write8(0x1070, 1); + mchbar_write8(0x1080, 6); if (sysinfo->gfx_type == GMCH_PM45) { - MCHBAR16(0x1001) = 0; - MCHBAR8(0x1007) = 0; - MCHBAR32(0x1010) = 0; - MCHBAR32(0x1014) = 0; - MCHBAR8(0x101c) = 0x98; - MCHBAR16(0x1041) = 0x9200; - MCHBAR8(0x1047) = 0; - MCHBAR32(0x1050) = 0x2309; - MCHBAR32(0x1054) = 0; - MCHBAR8(0x105c) = 0x98; + mchbar_write16(0x1001, 0); + mchbar_write8(0x1007, 0); + mchbar_write32(0x1010, 0); + mchbar_write32(0x1014, 0); + mchbar_write8(0x101c, 0x98); + mchbar_write16(0x1041, 0x9200); + mchbar_write8(0x1047, 0); + mchbar_write32(0x1050, 0x2309); + mchbar_write32(0x1054, 0); + mchbar_write8(0x105c, 0x98); } else { - MCHBAR16(0x1001) = 0x9200; - MCHBAR8(0x1007) = 0; - MCHBAR32(0x1010) = 0x2309; - MCHBAR32(0x1014) = 0; - MCHBAR8(0x101c) = 0x98; - MCHBAR16(0x1041) = 0; - MCHBAR8(0x1047) = 0; - MCHBAR32(0x1050) = 0; - MCHBAR32(0x1054) = 0; - MCHBAR8(0x105c) = 0x98; + mchbar_write16(0x1001, 0x9200); + mchbar_write8(0x1007, 0); + mchbar_write32(0x1010, 0x2309); + mchbar_write32(0x1014, 0); + mchbar_write8(0x101c, 0x98); + mchbar_write16(0x1041, 0); + mchbar_write8(0x1047, 0); + mchbar_write32(0x1050, 0); + mchbar_write32(0x1054, 0); + mchbar_write8(0x105c, 0x98); } - MCHBAR32(0x1010) |= 1 << 31; - MCHBAR32(0x1050) |= 1 << 31; - MCHBAR32(CxGTC(0)) |= 1 << 31; - MCHBAR32(CxGTC(1)) |= 1 << 31; + mchbar_setbits32(0x1010, 1 << 31); + mchbar_setbits32(0x1050, 1 << 31); + mchbar_setbits32(CxGTC(0), 1 << 31); + mchbar_setbits32(CxGTC(1), 1 << 31); if (sysinfo->gs45_low_power_mode) { - MCHBAR32(0x11b0) = 0xa000083a; + mchbar_write32(0x11b0, 0xa000083a); } else if (sysinfo->gfx_type == GMCH_GM49) { - MCHBAR32(0x11b0) = 0x2000383a; - MCHBAR16(0x1190) &= ~(1 << 15); + mchbar_write32(0x11b0, 0x2000383a); + mchbar_clrbits16(0x1190, 1 << 15); } else if ((sysinfo->gfx_type != GMCH_PM45) && (sysinfo->gfx_type != GMCH_UNKNOWN)) { - MCHBAR32(0x11b0) = 0xa000383a; + mchbar_write32(0x11b0, 0xa000383a); } switch (sysinfo->selected_timings.fsb_clock) { case FSB_CLOCK_667MHz: - MCHBAR32(0x11d0) = 0x0fd88000; + mchbar_write32(0x11d0, 0x0fd88000); break; case FSB_CLOCK_800MHz: - MCHBAR32(0x11d0) = 0x1303c000; + mchbar_write32(0x11d0, 0x1303c000); break; case FSB_CLOCK_1067MHz: - MCHBAR32(0x11d0) = 0x194a0000; + mchbar_write32(0x11d0, 0x194a0000); break; } - tmp = MCHBAR32(0x11d4) & ~0x1f; - MCHBAR32(0x11d4) = tmp | 4; + tmp = mchbar_read32(0x11d4) & ~0x1f; + mchbar_write32(0x11d4, tmp | 4); } |